Multi-stage sample rate converter
Architectures of multi-stage sample rate converters are disclosed. According to one aspect of the present invention, a received signal with a higher sampling rate is converted to a lower sampling rate. To prevent aliasing in the resultant signal, an anti-aliasing filter is introduced. The passband of the anti-aliasing filter is so adjusted according to the conversation rate of a sample rate converter. To keep the implementation relatively simple, the coefficients of the filter are kept constant. Therefore, the conversation rate of a sample rate converter is constrained in a limited range, thus requiring only a constant anti-aliasing filter. A series of halfband filters are then used to convert the signal to a desired sampling rate.
1. An integrated circuit providing an output signal, the integrated circuit comprising:
an anti-alias filter to receive an input signal with a first sampling rate;
a sample rate converter, coupled to the anti-alias filter, designed to have a converting ratio being greater than 1 but less than 2, wherein, whenever a ratio of sample rates of the input signal and the output signal is greater than 2, a half-band filter is used to reduce the ratio so that coefficients of the anti-alias filter are constant; and
one or more down-sampling converters coupled in series to the sample rate converter to further reduce the ratio of sample rates.
2. The integrated circuit as recited in claim 1 , further comprising a multi-port switch with a number of input ports, each receiving a converted signal from the sample rate converter and one of the one or more down-sampling converters.
3. The integrated circuit as recited in claim 2 , wherein the multi-port switch is controlled by a signal to determine which one of the input ports of the multi-port switch to be connected to an output of the multi-port switch.
4. The integrated circuit as recited in claim 1 , wherein the input signal has a higher sampling rate and is decimated to an output signal with a lower sampling rate via the integrated circuit.
5. The integrated circuit as recited in claim 4 , wherein the anti-aliasing filter is introduced to prevent aliasing in the output signal.
6. The integrated circuit as recited in claim 5 , wherein the integrated circuit is in a receiver to receive wireless signals compliant with a wireless specification allowing signals with multiple sample rates.
7. The integrated circuit as recited in claim 6 , wherein the wireless specification is WiMAX.
8. The integrated circuit as recited in claim 1 , wherein coefficients of the anti-alias are kept constant.
9. The integrated circuit as recited in claim 8 , wherein the converting ratio of the sample rate converter is greater than 1 but less than 2.
10. The integrated circuit as recited in claim 9 , wherein each of the one or more down-sampling converters is a half-band filter.
11. An integrated circuit providing an output signal, the integrated circuit comprising:
an anti-alias filter with a constant cut-off frequency to receive an input signal;
a sample rate converter, coupled to the anti-alias filter, designed to have a converting ratio being greater than 1 but less than 2;
a number of down-sampling filters coupled in series to the sample rate converter, the exact number of the down-sampling filters in use being determined by a ratio of sample rates of the input signal and the output signal to keep the converting ratio of the sample rate converter greater than 1 but less than 2.
12. The integrated circuit as recited in claim 11 , wherein R=the ratio of sample rates of the input signal and the output signal, and R is reduced by 2 for each of the down-sampling filters used till R is greater than 1 but less than 2.
13. The integrated circuit as recited in claim 12 , wherein the sample rate converter is implemented based on Lagrange polynomial interpolation and in Farrow structure.
14. The integrated circuit as recited in claim 11 , wherein the cut-off frequency of the anti-alias filter is directly determined by the converting ratio of the sample rate converter.
15. The integrated circuit as recited in claim 14 , wherein the cut-off frequency of the anti-alias filter is nearly constant because the converting ratio of the sample rate converter is in a limited range.