Drain extended MOS devices with self-aligned floating region and fabrication methods therefor
Semiconductor devices and manufacturing methods therefor are disclosed, in which a drain-extended MOS transistor comprises a self-aligned floating region proximate one end of the transistor gate and doped with a first type dopant to reduce channel hot carrier degradation, as well as an oppositely doped first source/drain laterally spaced from the first end of the gate structure in a semiconductor body. The device may further comprise a resurf region doped to a lower concentration than the floating region to facilitate improved breakdown voltage performance. A method of fabricating a drain-extended MOS transistor in a semiconductor device is disclosed, comprising providing first dopants to a floating region in a semiconductor body, which is self-aligned with the first end of a gate structure, and providing second dopants to source/drains of the semiconductor body, wherein the first and second dopants are different.
1. A method of fabricating a drain-extended MOS transistor in a semiconductor device, comprising:
forming a gate structure over a semiconductor body, the gate structure having first and second opposite ends;
providing first dopants to a floating region in the semiconductor body proximate the first end of the gate structure, the floating region being self-aligned with the first end of the gate structure;
providing second dopants to first and second source/drains of the semiconductor body, the first source/drain being laterally spaced from the first end of the gate structure, the second source/drain being proximate to or spaced from the second end of the gate structure, wherein one of the first and second dopants are p-type and the other of the first and second dopants are n-type; and
providing first dopants to a resurf region extending between the floating region and the first source/drain in the semiconductor body, wherein providing first dopants to the floating region comprises performing a first implantation process to implant p-type dopants into the floating region using a first implantation dose of about 2E12 cm −2 or more and wherein the first dopants are p-type and the second dopants are n-type;
wherein providing first dopants to the resurf region comprises performing the first implantation process to implant p-type dopants into the floating region and the resurf region using the first implantation dose, further comprising performing a second implantation process to implant n-type dopants into the resurf region using a second implantation dose, the second implantation dose being less than the first implantation dose.
2. The method of claim 1 , further comprising forming a first gate sidewall spacer over the semiconductor body before performing the second implantation process, the first gate sidewall spacer overlying at least a portion of the floating region and extending laterally outward from the first end of the gate structure.
3. A method of fabricating a drain-extended MOS transistor in a semiconductor device, comprising:
forming a gate structure over a semiconductor body, the gate structure having first and second opposite ends;
providing first dopants to a floating region in the semiconductor body proximate the first end of the gate structure, the floating region being self-aligned with the first end of the gate structure;
providing second dopants to first and second source/drains of the semiconductor body, the first source/drain being laterally spaced from the first end of the gate structure, the second source/drain being proximate to or spaced from the second end of the gate structure, wherein one of the first and second dopants are p-type and the other of the first and second dopants are n-type;
providing first dopants to a resurf region extending between the floating region and the first source/drain in the semiconductor body, wherein providing first dopants to the floating region comprises performing a first implantation process to implant p-type dopants into the floating region using a first implantation dose of about 5E12 cm −2 or more and wherein the first dopants are p-type and the second dopants are n-type, wherein providing first dopants to the floating region comprises providing a mask exposing the floating region and covering the resurf region while performing the first implantation process; and
wherein providing first dopants to the resurf region comprises:
forming a first gate sidewall spacer over the semiconductor body after the first implantation process, the first gate sidewall spacer overlying at least a portion of the floating region and extending laterally outward from the first end of the gate structure; and
performing a second implantation process after forming the first gate sidewall spacer to implant p-type dopants into the resurf region using a second implantation dose, the second implantation dose being less than the first implantation dose.
4. The method of claim 3 , wherein the second implantation dose is about 5E12 cm −2 or less.
5. The method of claim 4 , wherein the second implantation dose is about 1E12 cm −2 or more and about 4E12 cm −2 or less.