IP Library Granted Patent US 7,245,821
Granted Patent B2
US 7,245,821 · App. 10/156,912 · Granted Jul 17, 2007

Image processing using shared frame memory

Assignee: Sanyo Electric Co., Ltd.
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Quick Facts
Patent No.
US 7,245,821
App. No.
10/156,912
Granted
Jul 17, 2007
Kind
B2
Abstract

When a reverse reproduction is instructed, an MPEG video stream is once decoded and is again recoded by an MPEG video encoder so as to generate a recoded data sequence which will be overwritten on a storage area in a hard disk. An MPEG video decoder reads out this recoded data sequence in a reverse time-series manner and decodes it successively, and then converts it to a video signal so as to be outputted to a display.

Claims (13)

1. An image processing apparatus, comprising:

a front-end decoder which generates a first reproduced image data sequence by decoding a first coded data sequence including I picture, P picture and B picture coded in compliance with MPEG;

a first frame memory, utilized for a decoding processing by said front-end decoder, which stores the first reproduced image data sequence;

an encoder which generates a second coded data sequence by recoding the first reproduced image data sequence read out from said first frame memory;

a back-end decoder which generates a second reproduced image data sequence by decoding the second coded data sequence; and

a second frame memory, utilized for a decoding processing by said back-end decoder, which stores at least one picture included in the second reproduced image data sequence,

said first frame memory, including:

a first region which stores at least one I picture or one P picture to be front referred to for decoding P pictures or B pictures;

a second region which stores at least one I picture or one P picture to be back referred to for decoding B pictures; and

a third region, utilized for a decoding processing by said front-end decoder, which stores at least one B picture.

2. An image processing apparatus according to claim 1 , wherein processings for the decoding and the recoding are carried out in a predetermined unit of group.

3. An image processing apparatus according to claim 1 , wherein said first frame memory and second frame memory include a memory capacity equivalent to at least four frames in total.

4. A television receiver equipped with an image processing apparatus according to claim 1 , whereby reproduction of images in a reverse time-series manner is included as part of operational specifications thereof.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 24, 2014
From: SANYO ELECTRIC CO., LTD.
To: GODO KAISHA IP BRIDGE 1
Reel/Frame 032077/0337 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 28, 2002
From: OKADA, SHIGEYUKI
To: SANYO ELECTRIC CO., LTD.
Reel/Frame 012948/0029 →
Priority Claims (1)
JP 2001-165943 · May 31, 2001 · national
Continuity (1)
Related Publication 20020196858A1 · Dec 26, 2002