Fast pre-charge circuit and method of providing same for memory devices
A fast pre-charge circuit and method of providing a fast pre-charge for an integrated circuit memory device is disclosed. The fast pre-charge circuit comprises an address calculating unit and a multi-power driver. The address calculating unit detects the sector distance from driver of the integrated circuit memory device, and the driver provides a voltage to the loading of the integrated circuit memory device based on an output of the address calculating unit. Unlike a conventional fixed-power wordline driver, the driver of the present invention provides multiple voltage levels to the wordline or dynamically adjusts for different loading situations.
1. A pre-charge circuit for an integrated circuit memory device, comprising:
an address calculating unit to detect a loading of said integrated circuit memory device; and a driver to provide a voltage to said loading of said integrated circuit memory device based on an output of said address calculating unit.
2. The pre-charge circuit for an integrated circuit memory device according to claim 1 , wherein said loading is a wordline.
3. The pre-charge circuit for an integrated circuit memory device according to claim 1 , wherein said loading is a bitline.
4. The pre-charge circuit for an integrated circuit memory device according to claim 1 , wherein said loading can be defined with a plurality of sectors.
5. The pre-charge circuit for an integrated circuit memory device according to claim 4 , wherein said driver provides said voltage with multiple voltage levels to said loading.
6. The pre-charge circuit for an integrated circuit memory device according to claim 4 , wherein said driver provides a higher voltage level to a sector with a heavier loading or with a longer distance from driver.
7. The pre-charge circuit for an integrated circuit memory device according to claim 1 , wherein said driver dynamically changes a voltage level of said voltage to said loading.
8. A method of providing a power to a pre-charge circuit for an integrated circuit memory device, comprising the steps of:
decoding an address of a line to be provided said power;
detecting a loading of said line; and
providing a voltage to said line based on said loading.
9. The method according to claim 8 , wherein said line is a wordline.
10. The method according to claim 8 , wherein said line is a bitline.
11. The method according to claim 8 , further comprises a step of calculating a distance from a driver of said line.
12. The method according to claim 8 , wherein said line can be defined to have a plurality of sectors.
13. The method according to claim 12 , wherein said voltage comprises multiple voltage levels.
14. The method according to claim 12 , wherein a higher voltage level is provided to a sector with a heavier loading.
15. The method according to claim 11 , wherein a higher voltage level is provided to a sector with a longer distance from said driver.
16. The method according to claim 8 , wherein said voltage to said loading is dynamically changed to a voltage level.
17. A method of providing a power to a pre-charge circuit for an integrated circuit memory device, comprising the steps of:
decoding an address of a wordline to be provided said power;
detecting a loading of said wordline; and
providing a voltage to said wordline based on said loading.
18. The method according to claim 17 , further comprises a step of calculating a distance from a driver of said line.
19. The method according to claim 17 , wherein said detecting is performed by a bitline address calculating circuit.
20. The method according to claim 19 , wherein said providing a voltage to said wordline is performed by a wordline multi-power driver.
21. The method according to claim 17 , wherein said wordline has a plurality of sectors.
22. The method according to claim 21 , wherein said voltage comprises multiple voltage levels.
23. The method according to claim 21 , wherein a higher voltage level is provided to a sector with a heavier loading.
24. The method according to claim 18 , wherein a higher voltage level is provided to a sector with a longer distance from said driver.
25. The method according to claim 17 , wherein said voltage to said loading is dynamically changed to a voltage level.
26. A method of providing a power to a pre-charge circuit for an integrated circuit memory device, comprising the steps of:
decoding an address of a bitline to be provided said power;
detecting a loading of said bitline; and
providing a voltage to said bitline based on said loading.
27. The method according to claim 26 , further comprises a step of calculating a distance from a driver of said line.
28. The method according to claim 26 , wherein said detecting is performed by a wordline address calculating circuit.
29. The method according to claim 26 , wherein said providing a voltage to said bitline is performed by a bitline multi-power driver.
30. The method according to claim 26 , wherein said bitline has a plurality of sectors.
31. The method according to claim 30 , wherein said voltage comprises multiple voltage levels.
32. The method according to claim 30 , wherein a higher voltage level is provided to a sector with a heavier loading.
33. The method according to claim 27 , wherein a higher voltage level is provided to a sector with a longer distance from said driver.
34. The method according to claim 26 , wherein said voltage to said loading is dynamically changed to a voltage level.