Methods and apparatus for error correction of transparent GFP (Generic Framing Procedure) superblocks

1. A method for correcting errors in a GFP-T (generic framing procedure-transparent mode) superblock having 64 bytes of data, a flag byte, and a 16 bit CRC, comprising:

receiving the GFP-T superblock:

buffering the 64 bytes of data in one buffer;

buffering the flag byte in a separate buffer;

calculating the CRC remainder;

comparing the CRC remainder to a single bit error syndrome table;

correcting a single bit error if the CRC remainder matches an entry in the single bit error syndrome table;

comparing the CRC remainder to a double bit error syndrome table;

correcting a double bit error if the CRC remainder matches an entry in the double bit error syndrome table; and

outputting a corrected 64 bytes of data, wherein

the flag byte is processed first and the data bytes are processed eight bytes at a time.

2. The method according to claim 1 , wherein:

the method is performed in three stages,

in the first stage the flag byte and the data are subjected to single bit error correction,

in the second stage the flag byte is subjected to second error double bit error correction and the data is subjected to first error double bit error correction, and

in the third stage the data is subjected to second error double bit error correction.

3. An apparatus for correcting errors in a GFP-T (generic framing procedure-transparent mode) superblock having 64 bytes of data, a flag byte, and a 16 bit CRC, comprising:

a data buffer for buffering the 64 bytes of data;

a flag byte buffer for buffering the flag byte;

a CRC calculation circuit for calculating the CRC remainder;

a single bit error syndrome table;

first comparison logic coupled to said CRC calculation circuit and to said single bit error syndrome table;

single bit error correction logic coupled to said data buffer, said flag byte buffer, and to said first comparison logic;

a double bit error syndrome table;

second comparison logic coupled to said CRC calculation circuit and to said double bit error syndrome table;

double bit error correction logic coupled to said single bit error correction logic and to said second comparison logic, wherein

the flag byte is processed first and the data bytes are processed eight bytes at a time.

4. The apparatus according to claim 3 , wherein:

said double bit error correction logic includes

first error correction logic coupled to said single bit error correction logic and to said

second comparison logic, and

second error correction logic coupled to said first error correction logic and to said

second comparison logic, and wherein

the flag byte and the data are subjected to single bit error correction by said single bit error correction logic,

the flag byte is subjected to second error double bit error correction by said first error correction logic,

the data is subjected to first error double bit error correction by said first error correction logic, and

the data is subjected to second error double bit error correction by said second error correction logic.

5. The apparatus according to claim 4 , wherein:

said double bit error correction logic includes a second error position calculation logic coupled to said second comparison logic and said second error correction logic.

6. An apparatus for correcting errors in a GFP-T (generic framing procedure-transparent mode) superblock having 64 bytes of data, a flag byte, and a 16 bit CRC, comprising:

a data buffer means for buffering the 64 bytes of data;

a flag byte buffer means for buffering the flag byte;

a CRC calculation circuit means for calculating the CRC remainder;

a single bit error syndrome table means for indicating the location of a single bit error;

first comparison logic means coupled to said CRC calculation circuit means and to said single bit error syndrome table means, said first comparison logic means for determining whether the CRC remainder matches an entry in said single bit error syndrome table means;

single bit error correction logic means coupled to said data buffer means, said flag byte buffer means, and to said first comparison logic means, said single bit error correction logic means for correcting a single bit error indicated by said first comparison logic means;

a double bit error syndrome table means for indicating the location of a first error of a double bit error;

second comparison logic means coupled to said CRC calculation circuit means and to said double bit error syndrome table means, said second comparison logic means for determining whether the CRC remainder matches an entry in said double bit error syndrome table means;

double bit error correction logic means coupled to said single bit error correction logic means and to said second comparison logic means, said double bit error correction logic means for correcting a double bit error indicated by said second comparison logic means, wherein

the flag byte is processed first and the data bytes are processed eight bytes at a time.

7. The apparatus according to claim 6 , wherein:

said double bit error correction logic means includes

first error correction logic means coupled to said single bit error correction logic means and to said second comparison logic means, said first error correction logic means for correcting one error of a double bit error, and

second error correction logic means coupled to said first error correction logic means and to said second comparison logic means, and wherein

the flag byte and the data are subjected to single bit error correction by said single bit error correction logic means,

the flag byte is subjected to second error double bit error correction by said first error correction logic means,

the data is subjected to first error double bit error correction by said first error correction logic means, and

the data is subjected to second error double bit error correction by said second error correction logic means.

8. The apparatus according to claim 7 , wherein:

said double bit error correction logic means includes a second error position calculation logic means coupled to said second comparison logic means and said second error correction logic means, said second error position logic means for determining the location of a second error double bit error.