Architecture of an integrated circuit for streaming media over wireless networks

1. An integrated circuit comprising: a baseband processor capable of facilitating wireless communication via a RF interface in more than one wireless standards, wherein the baseband processor includes a plurality of functional blocks to process signals that are received or to be transmitted; and a mode controller configured to control at least one of the functional blocks so the baseband processor performs to facilitate wireless communications in more than one wireless communication standards; a media module designed for processing media data that is coupled to or from the baseband processor; and switching means for avoiding non-media data being processed in the media module.

2. The integrated circuit as recited in claim 1 , wherein the media module includes a codec that converts digitized video and audio signals to video and audio data according to a video standard.

3. The integrated circuit as recited in claim 2 , wherein the video and audio data is processed in an application specific QoS control processing unit before being processed in the baseband processor.

4. The integrated circuit as recited in claim 1 , wherein the media module includes a codec that converts video and audio data from the baseband processor to digitized video and audio signals according to a video standard.

5. The integrated circuit as recited in claim 4 , wherein the video and audio data is processed in an application specific QoS control processing unit before being processed in the codec.

6. The integrated circuit as recited in claim 1 , wherein the mode controller is configured to provide a first mode and a second mode, the integrated circuit supports Wi-Fi communication when the mode controller commands the first mode, the integrated circuit supports WiMAX communication when the mode controller commands the second mode.

7. The integrated circuit as recited in claim 6 , wherein the functional blocks includes a RS codec that is deactivated when the mode controller commands the first mode.

8. The integrated circuit as recited in claim 7 , wherein the RS codec is coupled between a scrambler and a convolution encoder, but signals are coupled between the scrambler and the convolution encoder.

9. The integrated circuit as recited in claim 8 , wherein a multiplexer is provided to ensure that signals are received from the scrambler.

10. The integrated circuit as recited in claim 6 , wherein the functional blocks includes a RS codec that is activated when the mode controller commands the second mode.

11. The integrated circuit as recited in claim 10 , wherein the RS codec is coupled between a scrambler and a convolution encoder, and signals are coupled from the RS codec to the convolution encoder.

12. The integrated circuit as recited in claim 11 , wherein a multiplexer is provided to ensure that signals are received from the RS codec.

13. The integrated circuit as recited in claim 6 , wherein the functional blocks include

at least a FIFO buffer;

a first circuit, coupled to the FIFO buffer, performing either scramblering or unscramblering;

a second circuit performing either convolution encoding or Viterbi decoding;

a RS codec coupled between the first circuit and the second circuit;

a third circuit performing either interleaving or de-interleaving;

a forth circuit performing either modulating or demodulating, wherein the third circuit couples the second circuit to the forth circuit;

an FFT engine coupled to the firth circuit; and

a filter to ensure outgoing signals compliant with a communication standard, and filter out unwanted signals from incoming signals.

14. The integrated circuit as recited in claim 13 further including an AGC control circuit to control an RF interface to ensure that integrated circuit operates in a link-based mode or a packet-based mode.

15. The integrated circuit as recited in claim 13 , wherein the mode controller is configured to provide a first mode and a second mode, the integrated circuit supports Wi-Fi communication when the mode controller commands the first mode, the integrated circuit supports WiMAX communication when the mode controller commands the second mode.

16. The integrated circuit as recited in claim 15 , wherein the RS codec is activated or deactivated in response to the mode controller.

17. The integrated circuit as recited in claim 16 , wherein a multiplexer is used to select signals to facilitate the Wi-Fi communication or the WiMAX communication.

18. The integrated circuit as recited in claim 15 , wherein the mode controller is provided to control an operation mode of the integrated circuit, the mode controller receives a set of parameters from a memory in responding to a setting by a user to determine which mode the integrated circuit shall be operating.

19. The integrated circuit as recited in claim 15 , wherein the mode controller is provided to control an operation mode of the integrated circuit, the mode controller is configured to determine automatically which mode the integrated circuit shall be operating in responding to what type of signals is being received.