Image sensor with SOI substrate

1. A method of forming an imager pixel, comprising:

providing a silicon-on-insulator substrate, comprising a lower substrate portion, a buried oxide over said lower substrate portion, and a silicon layer over said buried oxide;

forming an n-type region in said lower substrate portion;

forming a p-type layer in said lower substrate portion and over said n-type region so as to form a photodiode;

forming an isolation border in said silicon layer;

forming pixel circuitry over said silicon layer; and

forming a dual contact in said substrate, said dual contact electrically connecting said photodiode to said pixel circuitry.

2. The method of claim 1 , wherein said dual contact comprises a first contact plug extending from said silicon layer to said n-type region and a second contact plug extending from said isolation border to said lower substrate portion, said first and second contact plugs being electrically connected.

3. The method of claim 1 , wherein said lower substrate portion, said n-type region, and said p-type layer form a pinned photodiode.

4. The method of claim 1 , wherein said isolation border defines a pixel area with respect to said substrate and said n-type region is formed to substantially span said pixel area.

5. The method of claim 4 , wherein said n-type region spans about 95% of said pixel area.

6. The method of claim 1 , further comprising implanting boron into said buried oxide.

7. The method of claim 1 , further comprising implanting deuterium into said buried oxide.

8. The method of claim 1 , further comprising implanting fluorine into said buried oxide.

9. The method of claim 1 , wherein said isolation border is a shallow trench isolation region.

10. The method of claim 1 , wherein said isolation border is a diffused isolation region.

11. The method of claim 2 , further comprising connecting said first and second contact plugs with a conductive strap.

12. The method of claim 2 , further comprising forming a p-type doped region in said substrate around said first and second contact plugs.

13. The method of claim 1 , wherein said pixel circuitry comprises a transfer transistor, a reset transistor, a source follower transistor, and a row select transistor.

14. The method of claim 1 , wherein said pixel is a CMOS pixel.

15. The method of claim 1 wherein said substrate comprises an epitaxial material.

16. The method of claim 15 , wherein said epitaxial material is a p-on-p+epi material.

17. The method of claim 16 , wherein said p+epi is a graded-epi layer.

18. The method of claim 15 , wherein said epitaxial material is an n-on-n+epi material.

19. The method of claim 18 , wherein said n+epi material is a graded-epi layer.

20. The method of claim 1 , further comprising forming at least a second n-type region in said lower substrate portion so as to form a second photodiode.

21. The method of claim 20 , wherein said photodiode is formed in said substrate so as to sense a first color of light and said second photodiode is formed in said substrate to sense a second color of light.

22. The method of claim 1 , further comprising forming a second and third photodiode in said lower substrate portion.

23. The method of claim 22 , wherein said photodiode is formed in said substrate so as to sense a first color of light, said second photodiode is formed in said substrate to sense a second color of light, and said third photodiode is formed in said substrate so as to sense a third color of light.

24. The method of claim 1 , wherein said n-type region and said p-type layer are configured so that said imager pixel senses light from a side of said lower substrate portion opposite said buried oxide and silicon layer.

25. A method of forming a CMOS imager pixel, comprising:

providing a silicon substrate and forming a buried oxide therein;

implanting a first dopant into said buried oxide;

implanting a second dopant into said substrate below said buried oxide to form an n-type region;

forming an isolation region in said substrate over said buried oxide and surrounding the pixel, wherein said n-type region substantially spans an area relative to said substrate defined by said isolation region;

forming pixel circuitry over said substrate;

etching said substrate to expose a portion of said n-type region in first via and a portion of said substrate under said isolation region in a second via;

implanting a third dopant into said substrate where exposed by said first and second vias;

forming a first conductive plug in said first via and a second conductive plug in said second via; and

forming a metal layer connecting said first and second conductive plugs.

26. The method of claim 25 , wherein said second dopant comprises boron.

27. The method of claim 26 , wherein said boron forms a p-type layer in said substrate over said n-type region.

28. The method of claim 25 , wherein said second dopant comprises deuterium.

29. The method of claim 25 , wherein said second dopant comprises fluorine.

30. The method of claim 25 , wherein said isolation region is a shallow trench isolation region.

31. The method of claim 25 , wherein said isolation region is a diffused isolation region.

32. The method of claim 25 , wherein said pixel circuitry comprises a transfer transistor, a reset transistor, a source follower transistor, and a row select transistor.

33. The method of claim 25 , wherein said substrate comprises a p-on-p+epi material.

34. The method of claim 33 , wherein said p+epi is a graded-epi layer.

35. The method of claim 25 , further comprising forming at least a second n-type region in said lower substrate portion.

36. The method of claim 35 , wherein said n-type region is formed in said substrate so as to sense a first color of light and said second n-type region is formed in said substrate to sense a second color of light.

37. The method of claim 25 , further comprising forming a second and third n-type region in said lower wafer portion.

38. The method of claim 37 , wherein said n-type region is formed in said substrate so as to sense a first color of light, said second n-type region is formed in said substrate to sense a second color of light, and said third n-type region is formed in said substrate to sense a third color of light.

39. The method of claim 25 , wherein said n-type region is configured so that said imager pixel senses light from a side of said lower wafer portion opposite said buried oxide and silicon layer.