CMOS (complementary metal oxide semiconductor) technology
View Patent ↗A method for forming semiconductor transistor. The method comprises providing a structure including (a) a semiconductor region, and (b) first and second dopant source regions on and in direct physical contact with the semiconductor region, wherein each region of the first and second dopant source regions comprises a dielectric material which contains dopants; causing the dopants to diffuse from the first and second dopant source regions into the semiconductor region so as to form first and second source/drain extension regions, respectively, wherein the first and second source/drain extension regions define a channel region disposed between; forming a gate dielectric region on a channel region; and forming a gate region on the gate dielectric region, wherein the gate dielectric region electrically insulates the gate region from the channel region.
1. A structure formation method, comprising:
providing a structure including:
(a) a semiconductor region comprising a semiconductor region top surface, and
(b) first and second dopant source regions on and in direct physical contact with the semiconductor region top surface, wherein each region of the first and second dopant source regions comprises a first dielectric material which contains first dopants;
forming a diffusion barrier region (i) on and in direct physical contact with the semiconductor region top surface and (ii) in direct physical contact with the first and second dopant source regions; then
causing the first dopants to diffuse from the first and second dopant source regions into the semiconductor region resulting in first and second source/drain extension regions, respectively, in the semiconductor region,
wherein the first and second source/drain extension regions define a channel region in the semiconductor region, and
wherein the channel region is (i) disposed between and in direct physical contact with the first and second source/drain extension regions and (ii) in direct physical contact with the semiconductor region top surface; then
removing the diffusion barrier region; then
forming a gate dielectric region on the channel region; and
forming a gate region on the gate dielectric region, wherein the gate dielectric region electrically insulates the gate region from the channel region.
2. The method of claim 1 , wherein the first dielectric material comprises boron silicate glass.
3. The method of claim 1 , wherein the first dielectric material comprises phosphorous silicate glass.
4. The method of claim 1 , further comprising forming a standard transistor on a wafer, wherein the structure is on the wafer, and wherein said forming the standard transistor comprises (a) forming a gate stack on the wafer, wherein the gate stack comprises (i) a gate dielectric layer and (ii) a gate electrode region, wherein the gate dielectric layer is sandwiched between and electrically insulates a channel portion in the wafer and the gate electrode region, then (b) forming first and second source/drain portions (i) in the wafer and (ii) aligned with the gate stack, and then (c) activating the first and second source/drain portions.
5. The method of claim 1 , wherein the gate dielectric region comprises a second dielectric material having a dielectric constant greater than 10.
6. The method of claim 1 , wherein the diffusion barrier region comprises a nitride material.
7. A structure formation method, comprising:
providing a structure including:
(a) a semiconductor region comprising a semiconductor region top surface, and
(b) first and second dopant source regions on and in direct physical contact with the semiconductor region top surface, wherein each region of the first and second dopant source regions comprises a first dielectric material which contains first dopants;
causing the first dopants to diffuse from the first and second dopant source regions into the semiconductor region so as to form first and second source/drain extension regions, respectively, in the semiconductor region,
wherein the first and second source/drain extension regions define a channel region in the semiconductor region, and
wherein the channel region is (i) disposed between and in direct physical contact with the first and second source/drain extension regions and (ii) in direct physical contact with the semiconductor region top surface;
forming a gate dielectric region on the channel region after said causing the first dopants to diffuse is performed;
forming a gate region on the gate dielectric region, wherein the gate dielectric region electrically insulates the gate region from the channel region; and
before said forming the gate dielectric region is performed:
creating first and second contact holes in the first and second dopant source regions, respectively; and
ion implanting second dopants in the semiconductor region via the first and second contact holes so as to form first and second source/drain regions, respectively, wherein the first and second source/drain regions are in direct physical contact with the first and second source/drain extension regions, respectively.
8. The method of claim 7 , wherein the first and second source/drain regions have a higher dopant concentration than that of the first and second source/drain extension regions.
9. The method of claim 7 , wherein the first dopants and the second dopants have a same dopant polarity.
10. The method of claim 7 , further comprising filling the first and second contact holes with an electrically conducting material so as to form first and second contact regions, respectively, wherein the gate region comprises the electrically conducting material.