Mixer circuits and methods with improved spectral purity

1. A mixer circuit comprising:

a first transistor having a gate, a source, and a drain;

a second transistor having a gate, a source, and a drain;

a first capacitance coupled between the source of the first transistor and the source of the second transistor; and

a bias circuit having an input, a first output coupled to the source of the first transistor and a second output coupled to the source of the second transistor, wherein the bias circuit includes a first resistor coupled to the source of the first transistor and a second resistor coupled to the source of the second transistor,

and wherein the first resistor is coupled between the source of the first transistor and a reference voltage and the second resistor is coupled between the source of the second transistor and the reference voltage.

2. The mixer circuit of claim 1 further comprising a second capacitance coupled to the source of the first transistor and a third capacitance coupled to the source of the second transistor.

3. The mixer circuit of claim 2 further comprising a voltage-to-current converter having an input that receives a voltage input signal and an output coupled to the second and third capacitance.

4. A mixer circuit comprising:

a first transistor having a gate, a source, and a drain;

a second transistor having a gate, a source, and a drain;

a first capacitance coupled between the source of the first transistor and the source of the second transistor; and

a bias circuit having an input, a first output coupled to the source of the first transistor and a second output coupled to the source of the second transistor, wherein the gates of the first and second transistors are coupled to a local oscillator, the bias circuit input is coupled to a digital-to-analog converter and the drains of the first and second transistors are coupled to a driver circuit for transmitting an RF signal.

5. A mixer circuit comprising:

a first transistor having a gate, a source, and a drain;

a second transistor having a gate, a source, and a drain;

a third transistor having a gate, a source, and a drain;

a fourth transistor having a gate, a source, and a drain;

a first capacitance coupled between the source of the first transistor and the source of the second transistor;

a second capacitance coupled between the source of the third transistor and the source of the fourth transistor; and

a bias circuit having first and second inputs, a first output coupled to the source of the first transistor, a second output coupled to the source of the second transistor, a third output coupled to the source of the third transistor, and a fourth output coupled to the source of the fourth transistor,

wherein the bias circuit comprises:

a first resistor having a first terminal coupled to the source of the first transistor and a second terminal coupled to a reference voltage;

a second resistor having a first terminal coupled to the source of the second transistor and a second terminal coupled to the reference voltage;

a third resistor having a first terminal coupled to the source of the third transistor and a second terminal coupled to the reference voltage; and

a fourth resistor having a first terminal coupled to the source of the fourth transistor and a second terminal coupled to the reference voltage.

6. The mixer circuit of claim 5 wherein the bias circuit comprises:

a fifth transistor having a gate, a source and a drain, wherein the gate receives a first voltage input signal and generates a first current output signal on the drain, and wherein the first current output signal is coupled to the source of the first transistor and the source of the second transistor; and

a sixth transistor having a gate, a source and a drain, wherein the gate receives a second voltage input signal that is a complement of the first voltage input signal and generates a second current output signal on the drain, and wherein the second current output signal is coupled to the source of the third transistor and the source of the fourth transistor.

7. The mixer circuit of claim 6 further comprising:

a third capacitor having a first terminal coupled to the source of the first transistor and a second terminal coupled to the drain of the fifth transistor;

a fourth capacitor having a first terminal coupled to the source of the second transistor and a second terminal coupled to the drain of the fifth transistor;

a fifth capacitor having a first terminal coupled to the source of the third transistor and a second terminal coupled to the drain of the sixth transistor; and

a fourth capacitor having a first terminal coupled to the source of the fourth transistor and a second terminal coupled to the drain of the sixth transistor.

8. A mixer circuit comprising:

a first transistor having a gate, a source and a drain;

a second transistor having a gate, a source and a drain;

a first capacitor coupled between the source of the first transistor and the source of the second transistor;

a first resistor having a first terminal coupled to the source of the first transistor and a second terminal coupled to a first reference voltage;

a second resistor having a first terminal coupled to the source of the second transistor and a second terminal coupled to the first reference voltage;

a second capacitor having a first terminal coupled to the source of the first transistor; and

a third capacitor having a first terminal coupled to the source of the second transistor.

9. The mixer circuit of claim 8 further comprising a third transistor having a gate, a source and a drain, wherein the gate receives a voltage input signal and generates a current output signal on the drain, and wherein the current output signal is coupled a second terminal of the second capacitor and a second terminal of the third capacitor.

10. The mixer circuit of claim 8 further comprising:

a third resistor having a first terminal coupled to the drain of the first transistor and a second terminal coupled to a second reference voltage; and

a fourth resistor having a first terminal coupled to the drain of the second transistor and a second terminal coupled to the second reference voltage.

11. The mixer circuit of claim 8 wherein the gates of the first and second transistors are coupled to a local oscillator, the first and second resistors are coupled to a digital-to-analog converter and the drains of the first and second transistors are coupled to a driver circuit for transmitting an RF signal.

12. The mixer circuit of claim 8 further comprising:

a third transistor having a gate, a source and a drain;

a fourth transistor having a gate, a source and a drain;

a fourth capacitor coupled between the source of the third transistor and the source of the fourth transistor;

a third resistor having a first terminal coupled to the source of the third transistor and a second terminal coupled to the first reference voltage;

a fourth resistor having a first terminal coupled to the source of the fourth transistor and a second terminal coupled to the first reference voltage;

a fifth capacitor having a first terminal coupled to the source of the third transistor; and

a sixth capacitor having a first terminal coupled to the source of the fourth transistor.