High frequency digital oscillator-on-demand with synchronization
View Patent ↗A High Frequency Digital Oscillator contains a ring oscillator having an output fn, and having coarse and fine frequency adjustments, wherein the input signal f 1 is the input to both the ring oscillator and the High-Frequency Digital Oscillator, which has a multiplicity of output signals including f 2 , f 4 , and f 8 at one-half, one fourth, and one-eighth the frequency of fn respectively, and wherein an input gating signal causes the oscillator to start or stop, a signal fc=1/4*(f 4 ) causing a coarse frequency adjustment and a signal A=(1/f 1 −1/fc) making a fine adjustment, and by stopping the new output before the rising edge of f 1 ; and then restarting starting the new output at the rising edge of so that the output and input are synchronized.
1. A High Frequency Digital Oscillator comprising:
(a) a gated ring oscillator comprising an output signal sfn, having a frequency fn, and comprising coarse and fine frequency adjustments;
(b) means for inputting an input signal sf 1 , further connected to an input to the ring oscillator;
(c) a multiplicity of output signals further comprising signals sf 2 , sf 4 , and sf 8 having the frequency one-half, one-fourth, and one-eighth the frequency of signal sfn, respectively;
(d) an input gating signal causing the oscillator to start or stop;
(e) means for measuring the period p 1 =1/sf 1 further comprising a counter which measures the largest integral number of unadjusted ring oscillator periods Nu of signal sfn, which fit within the period p 1 ;
(f) a counter circuit generating signal sfc, having a frequency equal to one-fourth fn;
(g) means for making a coarse adjustment to the ring oscillator as a function of measured results of p 1 , comprising an adder which adds a predefined oscillator delay Δtd, corresponding to the value of Nu, to the coarse delay path, and wherein each different value of Nu has a different corresponding value Δtd;
(h) means for measuring time delay Δ=(1/f 1 )−(1/fc) further comprising a counter which counts the number n of individual time delays required, and further comprising a multiplicity of time delay circuits N 1 c disposed in series, each having a precise time delay period td, which are activated during the duration Δ, wherein n*td=Δ;
(i) means for making a fine adjustment, and thereby generating a new value of signal sfn, having a frequency of (new fn) as a function of Δ;
(j) means for generating signal sf 0 , having a frequency equal to one-fourth times (new fn);
(k) means for stopping sf 0 and new sfn before a rising edge of sf 1 ; and
(l) means for starting sf 0 and new sfn at the rising edge of sf 1 ,
so that sf 0 is synchronized with, and has the same frequency as sf 1 , sf 2 has a frequency equal to one half that of (new fn), and sf 4 has a frequency equal to f 0 , which is one-fourth that of (new fn).
2. The oscillator of claim 1 , wherein the time delay circuits further comprise latching circuits.
3. The oscillator of claim 2 , wherein the means for making a fine adjustment comprises means for generating a new delay Δ 1 c corresponding to total delays effected by the latching circuits N 1 c which are set.
4. The oscillator of claim 3 , further comprising means for inserting new delay Δ 1 c into the oscillator fine delay path of the loop.
5. The oscillator of claim 4 , wherein the means for generating signal sf 0 further comprises a digital counter.
6. The oscillator of claim 2 , wherein the means for making a fine adjustment to the ring oscillator further comprises a comparator circuit between sf 1 and new sf 0 , and further comprises means for deriving new sf 0 after the coarse adjustment of the oscillator frequency, thereby determining a leftover time Δt to be converted to fine delay Δf to be applied to the delay path of the oscillator.