IP Library › Granted Patent US 7,287,199
Granted Patent B2
US 7,287,199 · App. 10/813,020 · Granted Oct 23, 2007

Device capable of detecting BIOS status for clock setting and method thereof

Assignee: Giga-Byte Technology Co., Ltd.
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Quick Facts
Patent No.
US 7,287,199
App. No.
10/813,020
Granted
Oct 23, 2007
Kind
B2
Abstract

A method capable of detecting a status of a basic input/output system (BIOS) for setting a clock is applied to a clock generating device of a computer motherboard and sets the clock according to a signal status of the BIOS or a trigger signal. A device capable of detecting the BIOS status for setting the clock is also proposed. The device has a crystal oscillator, a frequency control unit, a phase-lock-loop (PLL) spread-spectrum unit electrically connected with the crystal oscillator and the frequency control unit, a memory unit having a clock setting value stored therein, a detection control unit electrically connected with the memory unit and used to detect a signal status, and a logic control unit electrically connected with the PLL spread-spectrum unit, the frequency control unit and the detection control unit.

Claims (13)

1. A device for setting a clock, which is a clock generating device of a computer motherboard, comprising:

a crystal oscillator;

a frequency control unit;

a phase-lock-loop (PLL) spread-spectrum unit electrically connected with the crystal oscillator and the frequency control unit;

a memory unit having a clock setting value stored therein;

a detection control unit electrically connected with the memory unit and used to detect a signal status; and

a logic control unit electrically connected with the PLL spread-spectrum unit, the frequency control unit and the detection control unit,

wherein the clock setting value stored in the memory unit is an operating clock value of the logic control unit stored in the memory unit by the detection control unit when the detection control unit detects a BIOS as working regularly.

2. The device as claimed in the claim 1 , wherein the memory unit is an electrically erasable programmable read-only memory (EEROM), an erasable programmable read-only memory (EROM) or a flash memory.

3. The device as claimed in the claim 1 , wherein the signal status detected by the detection control unit is an output signal status of a BIOS.

4. The device as claimed in the claim 1 , wherein the signal status detected by the detection control unit is a trigger signal status.

5. The device as claimed in the claim 1 , wherein the clock setting value stored in the memory unit is set by a BIOS.

6. The device as claimed in the claim 1 , wherein the clock setting value stored in the memory unit is a fixed value.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 31, 2004
From: CHANG, YEN SHENG
To: GIGA-BYTE TECHNOLOGY CO., LTD.
Reel/Frame 015158/0308 →
Continuity (1)
Related Publication 20050246586A1 · Nov 3, 2005