Programmable strength output buffer for RDIMM address register
A programmable strength output buffer intended for use within the address register of a memory module such as a registered DIMM (RDIMM). The output signals of an array of such buffers drive respective output lines that are connected to the address or control pins of several RAM chips. The programmable buffers vary the strength of at least some of the output signals in response to a configuration control signal, such that the output signals can be optimized for the loads to which they will be connected.
1. A Registered Dual-Inline Memory Module (RDIMM), comprising:
an address register, said register providing a plurality of output signals which drive respective output lines, at least some of which are connected to the address or control inputs of respective random-access memory (RAM) chips residing on said RDIMM;
a configuration control signal; and
an array of programmable strength output buffers within said register which provide respective ones of said output signals, said buffers arranged to receive said configuration control signal and to vary the strength of their respective output signals in response to said configuration control signal;
wherein said address register includes at least one input for receiving said configuration control signal and said at least one input on said address register comprises JEDEC-specified configuration control bits which are hardwired to logic levels on said RDIMM.
2. The RDIMM of claim 1 , wherein said at least one input further comprises additional configuration control bits which are hardwired to logic levels on said RDIMM via redundant address register pins.
3. A Registered Dual-Inline Memory Module (RDIMM), comprising:
an address register, said register providing a plurality of output signals which drive respective output lines, at least some of which are connected to the address or control inputs of respective random-access memory (RAN) chips residing on said RDIMM;
a configuration control signal; and
an array of programmable strength output buffers within said register which provide respective ones of said output signals, said buffers arranged to receive said configuration control signal and to vary the strength of their respective output signals in response to said configuration control signal;
wherein said configuration control signal is electrically programmed into a memory device that resides on said RDIMM and is provided to said address register via said address register's JEDEC-specified configuration control bits.
4. The RDIMM of claim 3 , wherein said configuration control signal is further provided to said address register via redundant address register pins.
5. A Registered Dual-Inline Memory Module (RDIMM), comprising:
an address register, said register providing a plurality of output signals which drive respective output lines, at least some of which are connected to the address or control inputs of respective random-access memory (RAM) chips residing on said RDIMM;
a configuration control signal; and
an array of programmable strength output buffers within said register which provide respective ones of said output signals, said buffers arranged to receive said configuration control signal and to vary the strength of their respective output signals in response to said configuration control signal;
wherein said configuration control signal is provided by the memory subsystem, and transmitted to said address register via said address register's JEDEC-specified configuration control bits.
6. The RDIMM of claim 5 , wherein said configuration control signal is further provided to said address register via redundant address register pins, and in turn to said redundant address register pins through redundant RDIMM connector pins.
7. A Registered Dual-Inline Memory Module (RDIMM), comprising:
an address register, said register providing a plurality of output signals which drive respective output lines, at least some of which are connected to the address or control inputs of respective random-access memory (RAM) chips residing on said RDIMM;
a configuration control signal; and
an array of programmable strength output buffers within said register which provide respective ones of said output signals, said buffers arranged to receive said configuration control signal and to vary the strength of their respective output signals in response to said configuration control signal;
wherein said address register is configurable for use with different raw cards in response to said configuration control signal.
8. A Registered Dual-Inline Memory Module (RDIMM), comprising:
an address register, said register providing a plurality of output signals which drive respective output lines, at least some of which are connected to the address or control inputs of respective random-access memory (RAM) chips residing on said RDIMM;
a configuration control signal; and
an array of programmable strength output buffers within said register which provide respective ones of said output signals, said buffers arranged to receive said configuration control signal and to vary the strength of their respective output signals in response to said configuration control signal;
wherein said programmable strength output buffers are arranged such that subsets of said output buffers are programmed to respective strengths in response to said configuration control signal.
9. A Registered Dual-Inline Memory Module (RDIMM), comprising:
an address register, said register providing a plurality of output signals which drive respective output lines, at least some of which are connected to the address or control inputs of respective random-access memory (RAM) chips residing on said RDIMM;
a configuration control signal; and
an array of programmable strength output buffers within said register which provide respective ones of said output signals, said buffers arranged to receive said configuration control signal and to vary the strength of their respective output signals in response to said configuration control signal;
wherein said programmable strength output buffers comprises a first output driver and at least one additional output driver, the outputs of which are summed to provide said buffer's output signal, said additional output drivers enabled and disabled in response to said configuration control signal.
10. The RDIMM of claim 9 , wherein the output of each of said output drivers has an associated output current such that the output current of a programmable strength output buffer's output signal is varied in response to said configuration control signal.
11. The RDTMM of claim 9 , wherein said configuration control signal comprises a plurality of output strength control bits, said additional output drivers enabled and disabled in response to a respective one of said output strength control bits.
12. The RDIMM of claim 11 , wherein each of said programmable strength output buffers receives a respective enable signal and each of said output drivers has an enable input and is enabled and disabled in response to a signal applied to said enable input, said buffer's first output driver enabled and disabled in response to said enable signal and said buffer's additional output drivers enabled and disabled in response to a logical combination of said enable signal and a respective one of said output strength control bits.
13. The RDIMM of claim 9 , wherein said configuration control signal comprises a plurality of output strength control bits and said output drivers are enabled and disabled in response to a respective one of said output strength control bits, said RDIMM arranged such that each of said programmable strength output buffers receives the same output strength control bits such that the strengths of the output signals provided by each of said buffers is approximately equal.
14. The RDIMM of claim 9 , wherein said configuration control signal comprises a plurality of output strength control bits and said output drivers are enabled and disabled in response to a respective one of said output strength control bits, said output buffers arranged such that each of said programmable strength output buffers receives different output strength control bits such that the strengths of the output signals provided by said buffers are individually programmable.
15. The RDIMM of claim 9 , wherein said configuration control signal comprises a plurality of output strength control bits and said output drivers are enabled and disabled in response to a respective one of said output strength control bits, said programmable strength output buffers grouped into subsets each of which receive different output strength control bits, the buffers of each subset receiving the same output strength control bits such that the strengths of the output signals provided by the buffers of said subset are approximately equal.
16. A registered DIMM (RDIMM), comprising:
an address register, said register providing a plurality of output signals which drive respective output lines, at least some of which are connected to the address or control inputs of respective random-access memory (RAM) chips residing on said DIMM;
a plurality of configuration control signals;
an array of programmable strength output buffers within said register which provide said output signals, said buffers and configuration control signals arranged such that subsets of said register's output signals are programmed to respective strengths in response to said configuration control signals.