Semiconductor memory device for storing multivalued data
Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining the first memory cells in the bit line direction.
1. A semiconductor memory device comprising:
a memory cell array configured by arranging a plurality of memory cells in a matrix, each of which is capable of having one of a 2 n (n is a natural number equal to 2 or more) number of threshold voltages and storing an n number of bits of data;
a plurality of bit lines, each of which is connected to said plurality of memory cells arranged in the column direction;
a plurality of word lines, each of which is connected to said plurality of memory cells arranged in the row direction;
an n number of flag cells which are selected at the same time when the memory cells are selected by each of the word lines; and
a control section which, when writing the data in a k-th page (2<k<n) composed of a k number of bits into the memory cells selected by the word line, writes specific data into a k number (2<k<=n) of the flag cells and which, when reading the data in an i-th page (i<=n) from the memory cells, determines from the data read from the i-th flag cell whether the k-th page has been written into the memory cells.
2. The semiconductor memory device according to claim 1 , wherein said plurality of memory cells arranged in the column direction are connected in series to configure a NAND cell.
3. The semiconductor memory device according to claim 1 , wherein the n number of flag cells includes a plurality of cells, respectively, each of cells stores the same logic level; and
the control section causes the plurality of cells to store the same logic level in a write operation and decides the output of the flag cells by a majority of the outputs of the plurality of cells.
4. A semiconductor memory device comprising:
a memory cell storing two bits data, the two bits data being stored in the memory cell one by one by first and second write operations;
a flag cell simultaneously selected with the memory cell, first logic level data of the flag cell being changed to second logic level data by the second write operation; and
a controller which reads data from the memory cell by a first read voltage at a first page read operation, and which outputs the data read by the first read voltage when the data of the second logic level is not written in the flag cell and reads data from the memory cell by a second read voltage when the data of the second logic level is written in the flag cell.
5. The device according to claim 4 , wherein the second read voltage is higher than the first read voltage.
6. A semiconductor memory device comprising:
a memory cell storing two bits data, the two bits data being stored in the memory cell one by one by first and second write operations;
a flag cell simultaneously selected with the memory cell, first logic level data of the flag cell being changed to second logic level data by the second write operation; and
a controller which reads data from the memory cell at a second page read operation, and which outputs data fixed to a constant logic level from the read data when the data of the flag cell is at the first logic level and outputs the data read from the memory cell when the data of the flag cell is at the second logic level.
7. A semiconductor memory device comprising:
a memory cell storing two bits data, the two bits data being stored in the memory cell one by one by first and second write operations;
a flag cell simultaneously selected with the memory cell, first logic level data of the flag cell being changed to second logic level data by the second write operation; and
a controller which reads data from the memory cell by the first read voltage at the second page read operation, and which outputs data fixed to a constant logic level from the read data when the data of the flag cell is at the first logic level and outputs data read from the memory cell by a second read voltage when the data of the flag cell is at the second logic level.
8. The device according to claim 7 , wherein the second read voltage is higher than the first read voltage.
9. A semiconductor memory device comprising:
a memory cell storing two bits data, the two bits data being stored in the memory cell one by one by first and second write operations;
a flag cell simultaneously selected with the memory cell, first logic level data of the flag cell being changed to second logic level data by the second write operation; and
a controller which reads data from the memory cell by a first read voltage at the first read operation, and which outputs data read from the memory cell by a second read voltage when data of the flag cell is at the first logic level and outputs data read from the memory cell by a first read voltage when the data of the flag cell is at the second logic level.
10. The device according to claim 9 , wherein the first read voltage is higher than the second read voltage.