Contact hole formation method
A contact hole formation method includes a process of depositing a BPSG film 4 on a semiconductor substrate 1 on which transistors are formed, a process of planarizing the BPSG film 4 , a process of depositing a dielectric film 5 on the BPSG film 4 , and a process of forming contact holes 8 through the BPSG film 4 and the dielectric film 5 so as to reach the semiconductor substrate 1 , in a case in which gate electrodes are densely formed in some areas and sparsely formed in other areas. The above-described contact hole formation method allows a thickness of the BPSG film 4 to be uniform irrespective of the density of the gate electrodes, whereby an etching rate becomes uniform over the entire area of the semiconductor device. Thus, it is possible to form contact holes having minimized variations in a contact resistance and a value of leakage current.
1. A method for forming a semiconductor device comprising:
forming a first group of gate electrodes on a first region of a substrate so that the first group of gate electrodes are densely arranged;
forming a second group of gate electrodes on a second region of the substrate so that the second group of gate electrodes are sparsely arranged;
forming a first dielectric film as a single layer on the first region and the second region of the substrate on which the gate electrodes are formed so that the first dielectric film fills entire spaces between the gate electrodes;
planarizing the first dielectric film;
forming a second dielectric film on the first dielectric film, the second dielectric film having an etching rate different from an etching rate of the first dielectric film; and then
forming contact holes to a uniform depth through the first dielectric film and the second dielectric film,
wherein an entire surface of the first dielectric film is continuous and higher than a top surface of the gate electrodes just prior to planarizing the first dielectric film, and
wherein planarizing the first dielectric film results in the first dielectric film having a uniform thickness at those portions through which said contact holes are formed.
2. The method of claim 1 , further comprising planarizing the second dielectric film before forming the contact.
3. The method of claim 1 , wherein the first dielectric film includes phosphorus.
4. The method of claim 1 , wherein the contact is connected to the substrate or a corresponding one of the gate electrodes.
5. The method of claim 1 , wherein a distance between at least two adjacent ones of the gate electrodes formed on the first region is 0.3 μm or less.
6. The method of claim 1 , further comprising heating the first dielectric film before the planarizing of the first dielectric film and after the forming of the first dielectric film.
7. The method of claim 1 , wherein the second dielectric film is a non-doped oxide film.
8. The method of claim 1 , wherein the first dielectric film is planarized by CMP.
9. The method of claim 1 , wherein planarizing the first dielectric film results in the entire surface of the first dielectric film continuing to be higher than the top surface pf the gate electrodes.
10. The method of claim 1 , wherein the first dielectric film is one selected from the group consisting of: a BPSG film, a PSG film, a BSG film, an oxide film which is formed by coating, a low dielectric constant film, an organic film, and a porous film.
11. The method of claim 1 , wherein the second dielectric film is a TEOS film or a silicon nitride film.
12. The method of claim 1 , wherein the etching rate of the first dielectric film is higher than the etching rate of the second dielectric film.
13. A method for forming a semiconductor device comprising:
forming a first interconnection, a second interconnection adjacent the first interconnection, and a third interconnection adjacent the second interconnection, on a substrate;
forming a first dielectric film as a single layer on the substrate so that the first dielectric film fills an entire space between the first and second interconnections and an entire space between the second and third interconnections;
planarizing a surface of the first dielectric film;
forming a second dielectric film on the surface of the first dielectric film, the second dielectric film having an etching rate different from an etching rate of the first dielectric film; and then
forming contact holes to a uniform depth through the first dielectric film and the second dielectric film;
wherein a distance between the first interconnection and the second interconnection is greater than a distance between the second interconnection and the third interconnection, and
wherein an entire surface of the first dielectric film is continuous and higher than a top surface of the first, second and third interconnections just prior to planarizing the first dielectric film, and
wherein planarizing the surface of the first dielectric film results in the first dielectric film having a uniform thickness at those portions through which said contact holes are formed.
14. The method of claim 13 , wherein a distance between at least two adjacent ones of the interconnections formed on the first region is 0.3μm or less.
15. The method of claim 13 , wherein the first dielectric film includes phosphorus.
16. The method of claim 13 , wherein the second dielectric film is a non-doped oxide film.
17. the method of claim 13 , wherein the first dielectric film is planarized by CMP.
18. The method of claim 13 , wherein planarizing the first dielectric film results in the entire surface of the first dielectric film continuing to be higher than the top surface of the interconnections.
19. The method of claim 13 , wherein the first dielectric film is one selected from the group consisting of: a BPSG film, a PSG film, a BSG film, an oxide film which is formed by coating, a low dielectric constant film, an organic film, and a porous film.
20. The method of claim 13 , wherein the second dielectric film is a TEOS film or a silicon nitride film.
21. The method of claim 13 , wherein the etching rate of the first dielectric film is higher than the etching rate of the second dielectric film.
22. A method for forming a semiconductor device comprising:
forming a plurality of interconnections on a substrate, the interconnections including first interconnections and a second interconnection, the first interconnections having a width different than a width of the second interconnection;
forming a first dielectric film on the substrate;
planarizing the first dielectric film;
forming a second dielectric film on the first dielectric film, the second dielectric film having an etching rate different from an etching rate of the first dielectric film; and then
forming contact holes to a uniform depth through the first dielectric film and the second dielectric film,
wherein an entire surface of the first dielectric film is continuous and higher than a top surface of the interconnections just prior to planarizing the first dielectric film, and
wherein planarizing the first dielectric film results in the first dielectric film having a uniform thickness at those portions through which said contact holes are formed.
23. The method of claim 22 , wherein the first dielectric film includes phosphorus.
24. The method of claim 22 , further comprisiong heating the first dielectric film before the planarizing the first dielectric film.
25. The method of claim 22 , wherein the first dielectric film is planarized by CMP.
26. The method of claim 22 , wherein planarizing the first dielectric film results in the entire surface of the first dielectric film continuing to be higher than the top surface of the interconnections.
27. The method of claim 22 , wherein the first dielectric film is one selected from the group consisting of: a BPSG film, a PSG film, a BSG film, an oxide film which is formed by coating, a low dielectric constant film, an organic film, and a porous film.
28. The method of claim 22 , wherein the second dielectric film is a TEOS film or a silicon nitride film.
29. The method of claim 22 , wherein the etching rate of the first dielectric film is higher than the the etching rate of the second dielectric film.
30. A method for forming a semiconductor device comprising:
forming a first group of gate electrodes on a first region of a substrate so that the first group of gate electrodes are densely arranged;
forming a second group of gate electrodes on a second region of the substrate so that the second group of gate electrodes are sparsely arranged;
forming a first dielectric film as a single layer on the first region and the second region of the substrate on which the gate electrodes are formed so that the first dielectric film fills entire spaces between the gate electrodes, the first dielectric film including phosphorus;
heating the first dielectric film;
planarizing the first dielectric film after the heating of the first dielectric film;
forming a second dielectric film on the planarized first dielectric film, the second dielectric film comprising a non-doped oxide film; and then
forming contact holes to a uniform depth through the first dielectric film and the second dielectric film,
wherein planarizing the first dielectric film results in the first dielectric film having a uniform thickness at those portions through which said contact holes are formed.
31. The method of claim 30 , wherein a distance between at least two adjacent gate electrodes formed on the first region is 0.3 μm or less.
32. The method of claim 30 , wherein substantially an entire surface of the first dielectric film is continuous and higher than a top surface of the first, second and third gate electrodes just prior to planarizing the first dielectric film.
33. The method of claim 30 , wherein the first dielectric film is planarized by CMP.
34. The method of claim 30 , wherein planarizing the first dielectric film results in the entire surface of the first dielectric film being higher than the top surface of the gate electrodes.
35. The method of claim 30 , wherein the first dielectric film is one selected from the group consisting of: a BPSG film, a PSG film, a BSG film, an oxide film which is formed by coating, a low dielectric constant film, an organic film, and a porous film.
36. The method of claim 30 , wherein the second dielectric film is a TEOS film or a silicon notride film.
37. The method of claim 30 , wherein an etching rate of the first dielectric film is higher than an etching rate of the second dielectric film.
38. A method for forming a semiconductor device comprising:
forming a first gate electrode, a second gate electrode adjacent the first gate electrode, and a third gate electrode adjacent the second gate electrode, on a substrate;
forming a first dielectric film as a single layer on the substrate so that the first dielectric film fills an entire space between the first and second gate electrodes and an entire space between the second and third gate electrodes;
planarizing a surface of the first dielectric film;
forming a second dielectric film on the surface of the first dielectric film, the second dielectric film having an etching rate different from an etching rate of the first dielectric film; and then
forming contact holes to a uniform depth through the first dielectric film and the second dielectric film;
wherein a distance between the first gate electrode and the second gate electrode is greater than a distance between the second gate electrode and the third gate electrode, and
wherein an entire surface of the first dielectric film is continuous and higher than a top surface of the first, second and third gate electrodes just prior to planarizing the first dielectric film, and
wherein planarizing the surface of the first dielectric film results in the first dielectric film having a uniform thickness at those portions through which said contact holes are formed.
39. The method of claim 38 , wherein the first dielectric film includes phosphorus.
40. The method of claim 38 , wherein the second dielectric film is a non-doped oxide film.
41. The method of claim 38 , wherein the contact is connected to the substrate, or to one of the first, second and third gate electrodes.
42. The method of claim 38 , wherein the distance between the second gate electrode and the third gate electrode is 0.3μm or less.
43. The method of claim 38 , further comprising planarizing the second dielectric film before forming the contact.
44. The method of claim 38 , further comprising heating the first dielectric film before the planarizing of the first dielectric film.
45. The method of claim 38 , wherein a space between the first gate electrode and the second gate electrode, and a space between the second gate electrode and the third gate electrode, are filled with the first dielectric film.
46. The method of claim 38 , wherein the second dielectric film is formed on the first dielectric film before forming a precipitate on a surface of the first dielectric film, and after the planarizing of the first dielectric film.
47. The method of claim 38 , wherein the forming the second dielectric film on the first dielectric film is performed within 24 hours after the planarizing the first dielectric film.
48. The method of claim 38 , further comprising eliminating a precipitate on a surface of the first dielectric film after planarizing the first dielectric film.
49. The method of claim 48 , wherein the precipitate is eliminated by using a solution.
50. The method of claim 38 , wherein the contact is composed of a conductive film.
51. The method of claim 38 , wherein the second dielectric film is a non-doped oxide film.
52. The method of claim 38 , wherein the first dielectric film is planarized by CMP.
53. The method of claim 38 , wherein planarizing the first dielectric film results in the entire surface of the first dielectric film continuing to be higher than the top surface of the first, second and third gate electrodes.
54. The method of claim 38 , wherein the first dielectric film is one selected from the group consisting of: a BPSG film, a PSG film, a BSG film, an oxide film which is formed by coating, a low dielectric constant film, an organic film, and a porous film.
55. The method of claim 38 , wherein the second dielectric film is a TEOS film or a silicon nitride film.
56. The method of claim 38 , wherein the etching rate of the first dielectric film is higher than the etching rate of the second dielectric film.
57. A method for forming a semiconductor device comprising:
forming a first interconnection, a second interconnection adjacent the first interconnection, and a third interconnection adjacent the second interconnection, on a substrate;
forming a first dielectric film as a single layer on the substrate so that the first dielectric film fills an entire space between the first and second interconnections and an entire space between the second and third interconnections;
planarizing a surface of the first dielectric film;
forming a second dielectric film on the surface of the first dielectric film, the second dielectric film having an etching rate differnt from an etching rate of the first dielectric film; and then
forming contact holes to a uniform depth through the first dielectric film and the second dielectric film;
wherein a distance between the first interconnection and the second interconnection is greater than a distance between the second interconnection and the third interconnection, and
wherein an entire surface of the first dielectric film is continuous and higher than a top surface of the first, second and third interconnections just prior to planarizing the first dielectric film, and
wherein planarizing the surface of the first dielectric film results in th first dielectric film having a uniform thickness at those portions through which said contact holes are formed.
58. The method of claim 57 , wherein the first dielectric film includes phosphorus.
59. The method of claim 57 , wherein the etching rate of the first dielectric film is higher than the etching rate of the second dielectric film.
60. The method of claim 57 , wherein the second dielectric film is a non-doped oxide film.
61. The method of claim 57 , wherein the contact is connected to the substrate or to one of the first, second and third interconnections.
62. The method of claim 57 , wherein the distance between the second interconnection and the third interconnection is 0.3 μm or less.
63. The method of claim 57 , further comprising planarizing the second dielectric film before forming the contact.
64. The method of claim 57 , wherein a space between the first interconnection and the second interconnection, and a space between the second interconnection and the third interconnection, are filled with the first dielectric film.
65. The method of claim 57 , wherein the first dielectric film is planarized by CMP.
66. The method of claim 57 , wherein planarizing the first dielectric film results in the entire surface of the first dielectric film continuing to be higher than the top surface of the first, second and third interconnections.
67. The method of claim 57 , wherein the first dielectric film is one selected from the group consisting of: a BPSG film, a PSG film, a BSG film, an oxide film which is formed by coating, a low dielectric constant film, an organic film, and a porous film.
68. The method of claim 57 , wherein the second dielectric film is a TEOS film or a silicon nitride film.