Tunneling-resistor-junction-based microscale/nanoscale demultiplexer arrays
View Patent ↗Various embodiments of the present invention are directed to demultiplexers that include tunneling resistor nanowire junctions, and to nanowire addressing methods for reliably addressing nanowire signal lines in nanoscale and mixed-scale demultiplexers. In one embodiment of the present invention, an encoder-demultiplexer comprises a number of input signal lines and an encoder that generates an n-bit-constant-weight-code code-word internal address for each different input address received on the input signal lines. The encoder-demultiplexer includes n microscale signal lines on which an n-bit-constant-weight-code code-word internal address is output by the encoder, where each microscale signal line carries one bit of the n-bit-constant-weight-code code-word internal address. The encoder-demultiplexer also includes a number of encoder-demultiplexer-addressed nanowire signal lines interconnected with the n microscale signal lines via tunneling resistor junctions, the encoder-demultiplexer-addressed nanowire signal lines each associated with an n-bit-constant-weight-code code-word internal address.
1. An encoder-demultiplexer comprising:
q input signal lines;
an encoder that generates an n-bit-constant-weight-code-code word internal address for each different input address received on the q input signal lines;
n microscale signal lines on which an n-bit-constant-weight-code-code word internal address is output by the encoder, each microscale signal line carries one bit of the n-bit-constant-weight-code code-word internal address; and
a number of encoder-demultiplexer-addressed signal lines interconnected with the n microscale signal lines via tunneling resistor junctions, the encoder-demultiplexer-addressed signal lines each associated with an n-bit-constant-weight-code-code word internal address.
2. The encoder-demultiplexer of claim 1 wherein the n microscale signal lines are selectively interconnected with the encoder-demultiplexer-addressed signal lines so that, when the encoder outputs a particular n-bit-constant-weight-code-code word internal address to the n microscale signal lines, a signal is input to an encoder-demultiplexer-addressed signal line associated with the n-bit-constant-weight-code-code word internal address that is distinguishable from signals input to all encoder-demultiplexer-addressed signal lines not associated with the n-bit-constant-weight-code-code word internal address.
3. The encoder-demultiplexer of claim 1 wherein the signal input to the encoder-demultiplexer-addressed signal line associated with the n-bit-constant-weight-code-code word internal address that is distinguishable from signals input to all encoder-demultiplexer-addressed signal lines not associated with the n-bit-constant-weight-code-code word internal address is a voltage signal of greater magnitude than voltage signals output to all encoder-demultiplexer-addressed signal lines not associated with the n-bit-constant-weight-code-code word internal address.
4. The encoder-demultiplexer of claim 1 wherein the signal input to the addressed signal line associated with the n-bit-constant-weight-code-code word internal address that is distinguishable from signals input to all addressed signal lines not associated with the n-bit-constant-weight-code-code word internal address is a voltage signal of smaller magnitude than voltage signals output to all addressed signal lines not associated with the n-bit-constant-weight-code-code word internal address.
5. The encoder-demultiplexer of claim 1 wherein the signal input to the addressed signal line associated with the n-bit-constant-weight-code-code word internal address that is distinguishable from signals input to all encoder-demultiplexer-addressed signal lines not associated with the n-bit-constant-weight-code-code word internal address is a current signal of greater magnitude than voltage signals output to all encoder-demultiplexer-addressed signal lines not associated with the n-bit-constant-weight-code-code word internal address.
6. The encoder-demultiplexer of claim 1 wherein the signal input to the encoder-demultiplexer-addressed signal line associated with the n-bit-constant-weight-code-code word internal address that is distinguishable from signals input to all encoder-demultiplexer-addressed signal lines not associated with the n-bit-constant-weight-code-code word internal address is a current signal of smaller magnitude than voltage signals output to all encoder-demultiplexer-addressed signal lines not associated with the n-bit-constant-weight-code-code word internal address.
7. The encoder-demultiplexer of claim 1 wherein the q input signal lines and the n microscale signal lines are microscale signal lines, the encoder is implemented in microscale or submicroscale logic, and the number of encoder-demultiplexer-addressed signal lines are nanowires.
8. The encoder-demultiplexer of claim 1 that, along with an additional encoder-demultiplexers, addresses nanoscale components of a nanoscale or mixed-scale device arranged in 3 or more logical dimensions.
9. The encoder-demultiplexer of claim 1 wherein the number of q signal-lines needed to address each encoder-demultiplexer-addressed signal line is given by:
q =ceiling(log 2 M )
where M corresponds to the number of n-bit-constant-weight-code-code words.
10. A method for addressing signal lines in a mixed microscale/nanoscale demultiplexer, the method comprising:
determining a number of signal lines that need to be addressed;
determining a signal margin needed between a signal output to a selected, addressed signal line and any signal output to a non-selected, addressed signal; and
implementing a tunneling-resistor-junction-based encoder-demultiplexer to address the number of signal lines.
11. The method of claim 10 wherein the signals are voltages.
12. The method of claim 10 wherein implementing a tunneling-resistor-junction-based encoder-demultiplexer to address the nanowires further comprises providing an encoder-demultiplexer having n microscale signal lines, on which an n-bit-constant-weight-code code-word internal address is output by a constant-weight-code-based encoder, interconnected with the signal lines, the signal lines each associated with an n-bit-constant-weight-code-code word internal address, and wherein the constant-weight-code-based encoder generates an n-bit-constant-weight-code-code word internal address for each different external address received on the signal lines.