Measuring and correcting non-linearity of an internal multi-bit analog-to-digital converter in a delta-sigma analog-to-digital converter

1. A method for testing a circuit that converts an applied analog input signal to a digital representation thereof, comprising:

(a) applying a constant DC value as the input signal;

(b) forming a sum of the constant DC value and a feedback signal;

(c) integrating the sum found in (b);

(d) generating a first digital approximation including the integrated sum found in (c); and

(e) generating the feedback signal, wherein the feedback signal allows ramping of the integrated sum and a reset of the ramping.

2. A method as in claim 1 , wherein the constant DC value is selected to adjust the rate of the ramping in (e).

3. A method as in claim 1 , wherein generating the feedback signal in (e) includes:

setting the feedback signal to a first value when the first digital approximation is below a threshold level; and

setting the feedback signal to a second value when the first digital approximation is above the threshold level.

4. A method as in claim 1 , further comprising:

(f) characterizing the first digital approximation.

5. A method as in claim 4 , wherein characterizing the first digital approximation includes determining the linearity of the first digital approximation.

6. A method as in claim 5 , wherein determining the linearity of the first digital approximation includes:

(g) determining a linear fit for each ramp in the first digital approximation;

(h) calculating the difference between each ramp and its corresponding linear fit to produce a non-linearity curve; and

(i) averaging the non-linearity curves found in (h) to produce a first average non-linearity curve for the first digital approximation.

7. A method as in claim 6 , further comprising:

calculating first corrected values for the first digital approximation;

storing the first corrected values in memory; and

substituting the first corrected values for the first digital approximation.

8. A method as in claim 7 , wherein the first corrected values are generated by subtracting the average non-linearity curve from the first digital approximation.

9. A method as in claim 1 , further comprising:

generating a second digital approximation including the integrated sum found in (c); and

characterizing the second digital approximation.

10. A method as in claim 9 , wherein characterizing the second digital approximation includes determining the linearity of the second digital approximation.

11. A method as in claim 10 , wherein characterizing the second digital approximation includes:

(j) determining a linear fit for each ramp in the second digital approximation;

(k) calculating the difference between each ramp and its corresponding linear fit to produce a non-linearity curve; and

(l) averaging the non-linearity curves found in (k) to produce a second average non-linearity curve.

12. A method as in claim 11 , further comprising:

calculating second corrected values for the second digital approximation;

storing the second corrected values in memory; and

substituting the second corrected values for the second digital approximation.

13. A method as in claim 1 , wherein applying a constant DC input value includes zeroing the input.

14. A method for testing a circuit that converts an applied analog input signal to a digital representation thereof, comprising:

(a) applying a constant DC value as the input signal;

(b) forming a sum of the constant DC value and a feedback signal;

(c) integrating the sum found in (b);

(d) generating a first digital approximation including the integrated sum found in (c);

(e) generating the feedback signal wherein the feedback signal allows ramping of the integrated sum;

(f) setting the feedback signal to a fixed value; and

(g) changing the constant DC value to reset the ramping of the integrated sum.

15. A method for characterizing an internal ADC within a delta-sigma ADC that converts an applied analog input signal to a digital representation thereof, comprising:

integrating the sum of a constant DC input and a variable value to create a ramp;

applying the ramp to a first internal ADC having a first input range;

generating a first digital approximation of the ramp; and

switching the variable value to reset the ramp to one end of the first input range.

16. A method as in claim 15 , wherein the variable value switches between two possible values.

17. A method as in claim 15 , further comprising:

determining the error due to quantization of the first digital approximation;

applying the error to a second internal ADC; and

generating a second digital approximation of the error.

18. A method as in claim 17 , wherein the linearity of at least one of the first and second digital approximations is determined.