Vertical LC tank device

1. A structure, comprising:

a set of wiring levels on top of a semiconductor substrate, each wiring level of said set of wiring levels comprising copper wires in a respective dielectric layer, top surfaces of said copper wires coplanar with top surfaces of said respective dielectric layers, said wiring levels stacked on top of each other from a lowest wiring level nearest said substrate to a highest wiring level furthest from said substrate;

an inductor comprised of copper in said highest wiring level, said inductor confined within a perimeter of a region of said highest wiring level, a top surface of said inductor coplanar with a top surface of a dielectric layer comprising said highest wiring level;

an electric shield comprised of a magnetic material in said lowest wiring level of said set of wiring levels, a top surface of said electric shield coplanar with a top surface of a dielectric layer comprising said lowest wiring level;

a p-n junction varactor formed in said substrate and isolated by shallow trench isolation formed in said substrate, said varactor aligned completely under said perimeter of said region of said highest wiring level;

an additional electric shield comprised of said magnetic material in a next-to-lowest wiring level of said set of wiring levels between said highest wiring level and immediately adjacent to said wiring level containing said electric shield, a top surface of said additional electric shield coplanar with a top surface of a dielectric layer comprising said next-to-lowest wiring level;

at least one additional wiring level of said set of wiring levels disposed between said highest wiring level and said next to lowest wiring level;

an integrated circuit, at least one semiconductor device of said integrated circuit formed in said substrate and aligned under said perimeter of said region of said highest wiring level, at least one wire in each wiring level of said set of wiring levels electrically connected to said integrated circuit;

wherein said electric shield comprises a set of electrically conductive and spaced apart parallel bars;

wherein said additional electric shield comprises a set of electrically conductive and spaced apart parallel bars; and

wherein said bars of said set of electrically conductive parallel bars of said additional electric shield are orientated perpendicular to said bars of said set of electrically conductive parallel bars of said electric shield.

2. The structure of claim 1 , further including:

at least one wire of said integrated circuit formed in said lowest wiring level of said set of wiring levels and passing under said perimeter of said region of said highest wiring level.

3. The structure of claim 1 , wherein said varactor comprises diodes.

4. The structure of claim 1 , wherein said varactor comprises FETs.

5. The structure of claim 1 , wherein said inductor and said varactor are electrically connected to form an LC tank circuit having no metal interconnections parallel to a top surface of said semiconductor substrate.

6. The structure of claim 1 , wherein said inductor includes a magnetic core.

7. The structure of claim 1 , wherein said integrated circuit includes a phase-lock loop circuit, said inductor comprising a portion of a voltage controlled oscillator of said phase-lock loop circuit.

8. The structure of claim 7 , wherein said phase lock loop circuit includes a phase detector, a charge pump and a forward frequency divider connected in series and further includes a feedback frequency divider connected between an input of said forward frequency divider and a input of said phase detector.