Semiconductor integrated circuit and a semiconductor device

1. A semiconductor integrated circuit having an LDMOS transistor formed over a first conductivity type semiconductor substrate,

the LDMOS transistor comprising:

a second conductivity type first well region formed in the first conductivity type semiconductor substrate;

a first conductivity type second well region formed in the first well region;

a second conductivity type third well region formed in the second well region;

a drain region formed in the second well region;

a source region formed in the third well region;

a gate electrode between the drain region and the source region;

an insulating layer formed between the gate electrode and the drain region,

wherein the first conductivity type refers to P type and the second conductivity type refers to N type, and the LDMOS transistor is of the P-channel type; and

a level shift circuit which uses the P-channel LDMOS transistor, the level shift circuit comprising:

a pair of N-channel differential input MOS transistors;

a pair of P-channel clamping MOS transistors which are coupled with the drains of the differential input MOS transistors respectively; and

a pair of P-channel load MOS transistors which are coupled with the sources of the clamping MOS transistors respectively,

wherein the P-channel clamping MOS transistors are the LDMOS transistors;

wherein the pair of load MOS transistors are cross-coupled, with the gate electrode of one load MOS transistor coupled with the drain electrode of the other load MOS transistor and the gate electrode of the other load MOS transistor coupled with the drain electrode of the one load MOS transistor; and

wherein, in response to a differential input supplied to the pair of differential input MOS transistors, a signal which is level-shifted with respect to the amplitude of the differential input is outputted from the source electrodes of the pair of clamping MOS transistors.

2. A semiconductor device constituting a stepdown switching regulator which has a first power MOS transistor and a second power MOS transistor, both power MOS transistors designed for push-pull operation, and a driver IC which generates a switching control signal to drive the first power MOS transistor and the second power MOS transistor for push-pull operation,

the driver IC comprising:

a first logical circuit which receives a clock signal with an amplitude determined by a first operating supply voltage, generates a switch control signal for the first power MOS transistor and operates at the first operating supply voltage;

a level shift circuit which shifts the amplitude of the clock signal to a second operating supply voltage having a higher level than the first operating supply voltage; and

a second logical circuit which receives output from the level shift circuit, generates a switch control signal for the second power MOS transistor, and operates at the second operating supply voltage;

wherein the first logical circuit turns On the first power MOS transistor after the second power MOS transistor is turned Off; and the second logical circuit turns On the second power MOS transistor after the first power MOS transistor is turned Off,

the level shift circuit comprising:

a pair of N-channel differential input MOS transistors;

a pair of P-channel clamping MOS transistors which are coupled with the drains of the differential input MOS transistors respectively; and

a pair of P-channel load MOS transistors which are coupled with the sources of the clamping MOS transistors respectively;

wherein the pair of load MOS transistors are cross-coupled, with the gate electrode of one load MOS transistor coupled with the drain electrode of the other load MOS transistor and the gate electrode of the other load MOS transistor coupled with the drain electrode of the one load MOS transistor;

wherein an inverted signal of the clock signal and a noninverted signal are inputted into the pair of differential input MOS transistors and in response to this input, a level-shifted signal with respect to the amplitude of the differential input is outputted from the source electrodes of the pair of clamping MOS transistors; and

wherein the P-channel clamping MOS transistors are LDMOS transistors, the LDMOS transistor comprising:

an N-type first well region formed in a P-type semiconductor substrate;

a P-type second well region formed in the first well region;

an N-type third well region formed in the second well region;

a drain region formed in the second well region;

a source region formed in the third well region;

a gate electrode between the drain region and the source region; and

an insulating layer formed between the gate electrode and the drain region.

3. The semiconductor device according to claim 2 , wherein the stepdown switching regulator is packaged into one package.

4. The semiconductor device according to claim 3 , wherein the differential input MOS transistor comprises:

an N-type fourth well region formed in a P-type semiconductor substrate;

a P-type fifth well region formed in the fourth well region;

a drain region formed in the fourth well region;

a source region formed in the fifth well region;

a gate electrode between the drain region and the source region; and

an insulating layer formed between the gate electrode and the drain region.

5. An electronic circuit having, on a packaging substrate, a microprocessor and a power supply circuit for supplying operating power to the microprocessor,

wherein the power supply circuit includes a plurality of semiconductor devices according to claim 3 .