IP Library Granted Patent US 7,364,985
Granted Patent B2
US 7,364,985 · App. 10/673,692 · Granted Apr 29, 2008

Method for creating electrical pathways for semiconductor device structures using laser machining processes

Assignee: Micron Technology, Inc.
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Quick Facts
Patent No.
US 7,364,985
App. No.
10/673,692
Granted
Apr 29, 2008
Kind
B2
Abstract

A method for creating electrical pathways for semiconductor device structures using laser machining processes is provided. The method of the present invention includes providing a semiconductor substrate and forming one or more depressions in the semiconductor substrate using laser machining processes. Optionally, a film may be deposited over the semiconductor substrate and the depressions may be formed therein. Subsequently, the semiconductor substrate and/or film are etched to smooth out the depressions and the depressions are then filled with an electrically conductive material. The electrically conductive material is then planarized down to the surface of the semiconductor substrate or film thereby isolating the electrically conductive material in the depressions.

Claims (47)

1. A method for creating at least one electrical pathway in a semiconductor device structure, comprising:

providing a semiconductor substrate;

ablating one or more depressions elongated to a length in a direction substantially parallel to a surface of the semiconductor substrate in and along the surface to define at least one electrical pathway extending along the surface, the length of each depression of the one or more depressions being greater than a width of each respective depression of the one or more depressions;

depositing an electrically conductive material over the surface of the semiconductor substrate and into the one or more depressions; and

planarizing the electrically conductive material at least to the surface of the semiconductor substrate to laterally isolate the electrically conductive material in the one or more depressions.

2. The method of claim 1 , further comprising etching the one or more depressions in the surface of the semiconductor substrate subsequent to ablating and prior to depositing the electrically conductive material over the surface of the semiconductor substrate.

3. The method of claim 1 , wherein providing the semiconductor substrate comprises providing at least one of a silicon wafer, a silicon on insulator substrate, a silicon on sapphire substrate, an epitaxial layer of silicon on a base semiconductor foundation, a substrate comprising a layer of silicon-germanium, a substrate comprising a layer of germanium, a substrate comprising a layer of gallium arsenide and a substrate comprising a layer of indium phosphide.

4. The method of claim 1 , wherein depositing the electrically conductive material over the surface of the semiconductor substrate comprises depositing at least one of a metal, a conductive polymer and conductive nano-particles over the surface of the semiconductor substrate.

5. The method of claim 4 , wherein depositing the at least one of the metal, the conductive polymer and the conductive nano-particles over the surface of the semiconductor substrate comprises depositing a metal selected from the group consisting of solder, aluminum, titanium, nickel, iridium, copper, gold, tungsten, silver, platinum, palladium, tantalum, molybdenum and alloys thereof over the surface of the semiconductor substrate.

6. The method of claim 4 , wherein depositing the at least one of the metal, the conductive polymer and the conductive nano-particles over the surface of the semiconductor substrate comprises depositing a conductive polymer selected from the group consisting of a metal filled silicone and an isotropically conductive or conductor-filled epoxy over the surface of the semiconductor substrate.

7. The method of claim 1 , wherein providing the semiconductor substrate comprises providing the semiconductor substrate and forming a film over at least a portion of the surface of the semiconductor substrate, and wherein ablating one or more depressions in the surface of the semiconductor substrate comprises ablating the one or more depressions at least partially through the film.

8. The method of claim 7 , further comprising:

depositing an electrically conductive material over a surface of the film and into the one or more depressions; and

planarizing the electrically conductive material at least to the surface of the film to laterally isolate the electrically conductive material in the one or more depressions.

9. The method of claim 8 , further comprising etching the one or more depressions in the film subsequent to ablating and prior to depositing the electrically conductive material over the surface of the film.

10. A method for creating at least one conductive element and at least one conductive structure in a semiconductor device structure, comprising:

providing a semiconductor substrate; and

substantially simultaneously ablating at least one depression elongated to a length in a direction substantially parallel to a surface of the semiconductor substrate in and along the surface to define a path for at least one conductive element in the form of an elongated trace extending along the surface of the semiconductor substrate, the length being greater than a width of the at least one depression, and ablating at least another depression in and transverse to the surface of the semiconductor substrate comprising a via extending into the semiconductor substrate.

11. The method of claim 10 , further comprising:

depositing an electrically conductive material over the surface of the semiconductor substrate and into the at least one depression and the at least another depression; and

planarizing the electrically conductive material at least to the surface of the semiconductor substrate to laterally isolate the electrically conductive material in the at least one depression and the at least another depression.

12. The method of claim 11 , further comprising etching the at least one depression and the at least another depression in the surface of the semiconductor substrate subsequent to ablating and prior to depositing the electrically conductive material over the surface of the semiconductor substrate.

13. The method of claim 10 , wherein providing the semiconductor substrate comprises providing at least one of a silicon wafer, a silicon on insulator substrate, a silicon on sapphire substrate, an epitaxial layer of silicon on a base semiconductor foundation, a substrate comprising a layer of silicon-germanium, a substrate comprising a layer of germanium, a substrate comprising a layer of gallium arsenide and a substrate comprising a layer of indium phosphide.

14. The method of claim 11 , wherein depositing the electrically conductive material over the surface of the semiconductor substrate comprises depositing at least one of a metal, a conductive polymer and conductive nano-particles over the surface of the semiconductor substrate.

15. The method of claim 14 , wherein depositing the at least one of the metal, the conductive polymer and conductive nano-particles over the surface of the semiconductor substrate comprises depositing a metal selected from the group consisting of solder, aluminum, titanium, nickel, iridium, copper, gold, tungsten, silver, platinum, palladium, tantalum, molybdenum and alloys thereof over the surface of the semiconductor substrate.

16. The method of claim 14 , wherein depositing the at least one of the metal, the conductive polymer and conductive nano-particles over the surface of the semiconductor substrate comprises depositing a conductive polymer selected from the group consisting of a metal filled silicone and an isotropically conductive or conductor-filled epoxy over the surface of the semiconductor substrate.

17. The method of claim 10 , wherein providing the semiconductor substrate comprises providing the semiconductor substrate and forming a film over at least a portion of the surface of the semiconductor substrate, and wherein ablating at least one depression and at least another depression in the surface of the semiconductor substrate comprises ablating the at least one depression and the at least another depression at least partially through the film.

18. The method of claim 17 , wherein ablating at least one depression and at least another depression at least partially through the film comprises ablating the at least one conductive structure precursor through the film to expose an active area on the surface of the semiconductor substrate.

19. The method of claim 17 , further comprising:

depositing an electrically conductive material over a surface of the film and into the at least one depression and the at least another depression; and

planarizing the electrically conductive material at least to the surface of the film to laterally isolate the electrically conductive material in the at least one depression and the at least another depression.

20. The method of claim 19 , further comprising etching the at least one depression and the at least another depression subsequent to ablating and prior to depositing the electrically conductive material over the surface of the film.

21. A method for creating at least one electrical connection through a sidewall of a semiconductor device structure, comprising:

providing a semiconductor substrate having an active surface, a backside surface, and at least one sidewall oriented substantially perpendicular to the active surface and the backside surface; and

ablating one or more depressions in a surface of the at least one sidewall of the semiconductor substrate to define at least one electrical connection.

22. The method of claim 21 , further comprising:

depositing an electrically conductive material over the surface of the at least one sidewall of the semiconductor substrate and into the one or more depressions; and

planarizing the electrically conductive material at least to the surface of the at least one sidewall of the semiconductor substrate to laterally isolate the electrically conductive material in the one or more depressions.

23. The method of claim 22 , further comprising etching the one or more depressions in the surface of the at least one sidewall of the semiconductor substrate subsequent to ablating and prior to depositing the electrically conductive material over the surface of the at least one sidewall of the semiconductor substrate.

24. The method of claim 21 , wherein providing the semiconductor substrate comprises providing the semiconductor substrate and forming a film over at least a portion of the surface of the at least one sidewall of the semiconductor substrate, and wherein ablating one or more depressions in the surface of the at least one sidewall of the semiconductor substrate comprises ablating the one or more depressions at least partially through the film.

25. The method of claim 24 , further comprising:

depositing an electrically conductive material over a surface of the film and into the one or more depressions; and

planarizing the electrically conductive material at least to the surface of the film to laterally isolate the electrically conductive material in the one or more depressions.

26. The method of claim 25 , further comprising etching the one or more depressions subsequent to ablating and prior to depositing the electrically conductive material over the surface of the film.

27. The method of claim 1 , wherein ablating one or more depressions in the surface of the semiconductor substrate further comprises:

providing a laser configured to emit a laser beam; and

traversing the surface of the semiconductor substrate with the laser beam.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 29, 2003
From: KIRBY, KYLE K.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 014570/0165 →
Continuity (1)
Related Publication 20050070092A1 · Mar 31, 2005