IP Library Granted Patent US 7,367,113
Granted Patent B2
US 7,367,113 · App. 11/278,952 · Granted May 6, 2008

Method for fabricating a transformer integrated with a semiconductor structure

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Quick Facts
Patent No.
US 7,367,113
App. No.
11/278,952
Granted
May 6, 2008
Kind
B2
Abstract

A substrate is provided and a top interconnection metal layer and a primary winding layer are formed thereon. Then a passivation layer having a plurality of via exposed parts of the top interconnection metal layer is formed on the substrate. A secondary winding layer and at least a bonding pad are formed on the passivation layer. The bonding pad electrically connects to the top interconnection metal layer through the via.

Claims (15)

1. A method for fabricating a transformer integrated with a semiconductor structure comprising:

providing a substrate;

simultaneously forming a top interconnection metal layer and a primary winding layer comprising a coil pattern on the substrate;

providing a space in between the top interconnection metal layer and the primary winding layer;

forming a passivation layer covering the top interconnection metal layer and the primary winding layer on the substrate, and the passivation layer further having a plurality of openings exposing parts of the top interconnection metal layer; and

simultaneously forming a secondary winding layer comprising a coil pattern and at least a bonding pad on the passivation layer, and the bonding pad being electrically connected to the top interconnection metal layer through the openings.

2. The method of claim 1 , wherein the substrate further comprises an active circuit and at least an interconnection metal layer.

3. The method of claim 1 , wherein the passivation layer has a thickness in a range of 100-500 angstroms.

4. The method of claim 1 , wherein the top interconnection metal layer and the primary winding layer are simultaneously formed by the copper interconnection technology.

5. The method of claim 1 , wherein the secondary winding layer comprises titanium, titanium oxide, aluminum, or alloys of the aforementioned metals.

6. The method of claim 1 , wherein the coil patterns of the primary winding layer and the secondary winding layer are partially overlapping.

7. The method of claim 6 , wherein the patterns of the primary winding layer and the secondary winding layer are preferably coaxial.

8. The method of claim 1 , wherein a width of the primary winding layer is smaller than a width of the secondary winding layer.

9. The method of claim 1 further comprising a step of forming a protection layer on the substrate, the protection layer covering the secondary winding layer and exposing the bonding pad.

10. The method of claim 9 , wherein the protection layer comprises silicon nitride.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2021
From: UNITED MICROELECTRONICS CORPORATION
To: MARLIN SEMICONDUCTOR LIMITED
Reel/Frame 056991/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 7, 2006
From: HUNG, CHENG-CHOU; TSENG, HUA-CHOU; LIANG, VICTOR-CHIANG; CHEN, YU-CHIA; HSU, TSUN-LAI
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 017433/0619 →