Magnetic random access memory device and method of forming the same
Example embodiments of the present invention disclose a semiconductor memory device and a method of forming a memory device. A semiconductor memory device may include a digit line disposed on a substrate, an intermediate insulating layer covering the digit line, a magnetic tunnel junction (MTJ) pattern disposed on the intermediate insulating layer and over the digit line, the MTJ pattern including a sequentially stacked lower magnetic pattern, upper magnetic pattern, and capping pattern, wherein the capping pattern does not react with the upper magnetic pattern at a temperature above about 280° C., and a bit line connected to the capping pattern and disposed to intersect the digit line. A method of forming a semiconductor memory device may include forming a digit line on a substrate, forming an intermediate insulating layer covering the digit line, forming a magnetic tunnel junction (MTJ) pattern on the intermediate insulating layer, the MTJ pattern including a sequentially stacked lower magnetic pattern, upper magnetic pattern, and capping pattern, wherein the capping pattern does not react with the upper magnetic pattern at a temperature above about 280° C., performing an annealing operation at a temperature of about 350° C. or higher, and forming a bit line connected to the capping pattern and disposed to intersect the digit line.
1. A semiconductor memory device, comprising:
a digit line disposed on a substrate;
an intermediate insulating layer covering the digit line;
a magnetic tunnel junction (MTJ) pattern disposed on the intermediate insulating layer and over the digit line, the MTJ pattern including a sequentially stacked lower magnetic pattern, an upper magnetic pattern, and a capping pattern, wherein the capping pattern does not react with the upper magnetic pattern at a temperature above about 280° C.; and
a bit line connected to the capping pattern and disposed to intersect the digit line.
2. The device of claim 1 , wherein the capping layer is formed of at least one material selected from a group consisting of zirconium, yttrium, and hafnium.
3. The device of claim 1 , wherein the MTJ pattern further includes a tunnel insulating layer between the stacked lower magnetic pattern and the upper magnetic pattern, and an anti-oxidation conductive pattern disposed on the capping pattern and connected to the bit line.
4. The device of claim 3 , wherein the tunnel insulating layer includes a magnesium oxide layer or an aluminum oxide layer.
5. The device of claim 1 , further including a Metal-Oxide-Semiconductor (MOS) transistor disposed beneath the digit line.
6. The device of claim 1 , wherein the lower magnetic pattern includes:
a pinning pattern;
a first pinned pattern disposed on the pinning pattern;
a reversing pattern disposed on the first pinned pattern; and
a second pinned pattern disposed on the reversing pattern,
wherein a magnetization direction of the first pinned pattern is fixed to a first direction by the pinning pattern, and the reversing pattern fixes a magnetization direction of the second pinned pattern in a second direction with respect to the fixed first magnetization direction of the first pinned pattern.
7. The device of claim 6 , wherein a thickness of the first pinned pattern is greater than a thickness of the second pinned pattern.
8. The device of claim 6 , wherein the lower magnetic pattern further includes a diffusion baffler pattern interposed between the pinning pattern and the first pinned pattern to prevent outward diffusion of elements in the pinning pattern.
9. The device of claim 6 , wherein the first pinned pattern includes an amorphous ferromagnet.
10. The device of claim 8 , wherein the first pinned pattern includes an amorphous ferromagnet.
11. The device of claim 1 , wherein the MTJ pattern is formed in a rectangular shape, and a magnetization direction of the upper magnetic pattern is parallel to a longitudinal direction of the MTJ pattern when magnetic fields are generated by the digit line and the bit line.
12. The device of claim 1 , further comprising:
a lower insulating layer interposed between the digit line and the substrate;
an electrode interposed between the MTJ pattern and the intermediate insulating layer;
a conductive plug disposed in the intermediate insulating layer; and
an upper insulating layer disposed above the intermediate insulating layer and surrounding the MTJ pattern,
wherein the MTJ pattern is connected at a first side of the electrode, and the conductive plug is connected to a second side of the electrode.