MIM capacitor in a semiconductor device and method therefor
A MIM capacitor is formed over one or more metal interconnect layers in a semiconductor device. The capacitor has a lower plate electrode and an upper plate electrode. An insulator is formed between the plate electrodes. Prior to forming the first plate electrode a first insulating layer is deposited over the metal of an interconnect layer. The first insulating layer is planarized using a chemical mechanical polish (CMP) process. A second insulating layer is then deposited over the planarized first insulating layer. The first plate electrode is formed over the second insulating layer. An insulator is formed over the first plate electrode and functions as the capacitor dielectric. A second plate electrode is formed over the insulator. Planarizing the first insulating layer and depositing a second insulating layer over the first insulating layer, reduces defects and produces a more reliable capacitor.
1. A method for forming a semiconductor device having a planar metal-insulator-metal (MIM) capacitor comprising:
providing a semiconductor substrate;
forming a plurality of layers of copper conductors over the semiconductor substrate, wherein a layer of the plurality of layers of copper conductors are formed over another layer of the plurality of layers of copper conductors, and each layer being separated from the semiconductor substrate and other layers of the plurality of layers of copper conductors by a plurality of inter-level dielectric layers;
forming a first insulating layer over the plurality of layers of copper conductors;
planarizing the first insulating layer;
forming a second insulating layer over the first insulating layer;
forming a first plate electrode for the planar MIM capacitor over the second insulating layer and directly over more than one conductor of each of the plurality of layers of copper conductors;
forming a third insulating layer over the first electrode; and
forming a second plate electrode for the planar MIM capacitor over the third insulating layer.
2. The method of claim 1 , wherein planarizing the first insulating layer comprises planarizing the first insulating layer using a chemical mechanical polishing process.
3. The method of claim 1 , further comprising:
forming a fourth insulating layer over the second plate electrode;
forming a plurality of conductors over the fourth insulating layer; and
electrically coupling the second plate electrode to one of the plurality of conductors.
4. The method of claim 1 , wherein the first insulating layer comprises tetraethyl orthosilicate (TEOS).
5. The method of claim 1 , wherein the third insulating layer comprises a high K dielectric formed to be between 20 to 1000 angstroms thick.
6. The method of claim 1 , wherein the MIM capacitor functions as a decoupling capacitor for the semiconductor device.
7. The method of claim 1 , wherein the MIM capacitor covers at least 50 percent of a surface area of the semiconductor device.
8. A method for forming a semiconductor device having a metal-insulator-metal (MIM) capacitor comprising:
providing a semiconductor substrate;
forming a plurality of copper interconnect layers over the semiconductor substrate, wherein each layer of the plurality of copper interconnect layers comprises a plurality of conductors and each layer of the plurality of copper interconnect layers is separated by a plurality of inter-level dielectric layers;
forming a first insulating layer over the plurality of copper interconnect layers;
planarizing the first insulating layer;
forming a second insulating layer over the first insulating layer;
forming a first plate electrode of the MIM capacitor over the second insulating layer and directly over more than one conductor of each of the plurality of copper interconnect layers;
forming a third insulating layer over the first electrode;
forming a second plate electrode of the MIM capacitor over the third insulating layer
forming a fourth insulating layer over the second plate electrode;
forming a plurality of conductors over the fourth insulating layer; and
electrically coupling the second plate electrode to one of the plurality of conductors.
9. The method of claim 8 , wherein planarizing the first insulating layer comprises planarizing the first insulating layer using a chemical mechanical polishing process.
10. The method of claim 8 , wherein the MIM capacitor functions as a decoupling capacitor for the semiconductor device.
11. The method of claim 8 , wherein the first insulating layer comprises tetraethyl orthosilicate (TEOS).
12. The method of claim 8 , wherein the third insulating layer comprises a high K dielectric formed to be between 20 to 1000 angstroms thick.
13. The method of claim 8 , wherein the MIM capacitor covers at least 50 percent of a surface area of the semiconductor device.
14. A semiconductor device comprising:
a semiconductor substrate;
a first inter-level dielectric layer formed over the semiconductor substrate;
a first interconnect layer comprising a first plurality of copper conductors formed over the first inter-level dielectric layer;
a second inter-level dielectric layer formed over the first copper interconnect layer;
a second interconnect layer comprising a second plurality of copper conductors formed over the second inter-level dielectric layer;
a first planarized insulating layer formed over the second interconnect layer;
a second insulating layer formed over the first insulating layer;
a first plate electrode formed over the second insulating layer and directly over at least two conductors of each of the first and second plurality of conductors;
a third insulating layer formed over the first electrode; and
a second plate electrode formed over the third insulating layer.
15. The semiconductor device of claim 14 , wherein the first planarized insulating layer is planarized using a chemical mechanical polishing process.