Semiconductor devices with dual-metal gate structures and fabrication methods thereof
View Patent ↗Semiconductor devices with dual-metal gate structures and fabrication methods thereof. A semiconductor substrate with a first doped region and a second doped region separated by an insulation layer is provided. A first metal gate stack is formed on the first doped region, and a second metal gate stack is formed on the second doped region. A sealing layer is disposed on sidewalls of the first gate stack and the second gate stack. The first metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a first metal layer on the high-k dielectric layer, a metal insertion layer on the first metal layer, a second metal layer on the metal insertion layer, and a polysilicon layer on the second metal layer. The second metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a second metal layer on the high-k dielectric layer, and a polysilicon layer on the second metal layer.
1. A complementary metal oxide semiconductor (CMOS) device with dual-metal gate structures, comprising:
a semiconductor substrate with a first doped region and a second doped region separated by an insulation;
a first metal gate stack on the first doped region layer;
a second metal gate stack on the second doped region;
a sealing layer disposed on sidewalls of the first gate stack and the second gate stack,
wherein the first metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a first metal layer on the high-k dielectric layer, a metal insertion layer on the first metal layer, a second metal layer on the metal insertion layer, and a polysilicon layer on the second metal layer, and
wherein the second metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a second metal layer on the high-k dielectric layer, and a polysilicon layer on the second metal layer.
2. The CMOS device according to claim 1 , wherein the interfacial layer comprises a substantial amount of Si, O, and N.
3. The CMOS device according to claim 1 , wherein the interfacial layer has a thickness ranging 0 and 3 nm.
4. The CMOS device according to claim 1 , wherein the interfacial layer comprises SiO 2 and SiO x N y .
5. The CMOS device according to claim 1 , wherein the interfacial layer comprises a nitrogen atomic ratio ranging from 1 to 15%.
6. The CMOS device according to claim 1 , wherein the high-k dielectric layer comprises a substantial amount of nitrogen.
7. The CMOS device according to claim 1 , wherein the high-k dielectric layer comprises single or multi-metal oxides or silicates comprising Hf, Al, Zr, La, or other metal elements.
8. The CMOS device according to claim 1 , wherein the high-k dielectric layer has a thickness ranging from 1 to 10 nm.
9. The CMOS device according to claim 1 , wherein the high-k dielectric layer comprises a silicon atomic ratio ranging from 10 to 90%.
10. The CMOS device according to claim 1 , wherein the high-k dielectric layer comprises HfO 2 or HfSiO x .
11. The CMOS device according to claim 1 , wherein the high-k dielectric layer is a nitrified high-k dielectric layer comprising a nitrogen atomic ratio ranging from 5 to 30%.
12. The CMOS device according to claim 11 , wherein the nitrified high-k dielectric layer has a thickness ranging from 1 to 10 nm.
13. The CMOS device according to claim 11 , wherein the nitrified high-k dielectric layer is HfSiO x N y with a silicon atomic ratio ranging from 10 to 90%.
14. The CMOS device according to claim 1 , wherein the high-k dielectric layer is substantially amorphous.
15. The CMOS device according to claim 1 , wherein the first metal layer and the second metal layer comprise metal, metal alloy, metal carbide, metal nitride, or conductive metal oxide.
16. The CMOS device according to claim 15 , wherein the first metal layer and the second metal layer are selected from different materials.
17. The CMOS device according to claim 1 , wherein both the first metal layer and the second metal layer have a thickness ranging from 1 to 30 nm.
18. The CMOS device according to claim 1 , wherein the first metal layer and the second metal layer comprises TaC x , TaN x , TiN x , Ru, RuO 2 , MoN x , MoO x N y , or WN.
19. The CMOS device according to claim 1 , wherein the metal insertion layer comprises metal, metal alloy, metal carbide, metal nitride, or conductive metal oxide.
20. The CMOS device according to claim 19 , wherein the metal insertion layer and the second metal layer are selected from the same material.
21. The CMOS device according to claim 1 , wherein the metal insertion layer has a thickness ranging from 1 to 10 nm.
22. The CMOS device according to claim 1 , wherein the metal insertion layer comprises TaC x , TaN x , or TiN x .
23. The CMOS device according to claim 1 , wherein the polysilicon layer has a thickness ranging from 30 to 200 nm.
24. The CMOS device according to claim 1 , wherein the sealing layer comprises an organic material or an inorganic material.
25. The CMOS device according to claim 1 , wherein the sealing layer has a thickness ranging from 1 to 20 nm.
26. The CMOS device according to claim 1 , wherein the sealing layer comprises silicon carbide or silicon nitride.