Method and apparatus for performing multiply-add operations on packed data

1. An apparatus comprising: a first input to receive a first packed data comprising at least four data elements a second input to receive a second packed data comprising at least four data elements; a multiply-adder circuit, responsive to a first instruction, to multiply a first pair of data elements of the first packed data by respective data elements of the second packed data and to generate a first result representing a first sum of products of said multiplications of said respective data elements with said first pair of data elements, and to multiply a second pair of data elements of the first packed data by respective data elements of the second packed data and to generate a second result representing a second sum of products of said multiplications of said respective data elements with said second pair of data elements; and an output to store a third packed data comprising at least said first and said results in response to the first instruction.

2. The apparatus of claim 1 wherein said first and second packed data each contain at least eight data elements.

3. The apparatus of claim 2 wherein said first and second packed data each contain at least 64-bits of packed data.

4. The apparatus of claim 2 wherein said first and second packed data each contain at least 128-bits of packed data.

5. The apparatus of claim 4 wherein said first and second packed data each contain at least sixteen data elements.

6. The apparatus of claim 4 wherein the first packed data comprises unsigned data elements.

7. The apparatus of claim 4 wherein the second packed data comprises signed data elements.

8. The apparatus of claim 7 wherein the first packed data comprises unsigned data elements.

9. The apparatus of claim 8 wherein the first and second results are generated using signed saturation.

10. The apparatus of claim 1 wherein the first and second results are truncated.

11. A computing system comprising: an addressable memory to store data; a processor including: a first storage area to store M packed data elements, the first storage area corresponding to a first N-bit source; a second storage area to store M packed data elements, the second storage area corresponding to a second N-bit source; a decoder to decode a first set of one or more instruction formats having a first field to specify the first N-bit source and a second field to specify the second N-bit source; an execution unit, responsive to the decoder decoding a first instruction of the first set of one or more instruction formats, to produce M products of multiplication of the packed data elements stored in the first storage area by corresponding packed data elements stored in the second storage area, and to sum the M products of multiplication pairwise to produce M/2 results representing M/2 sums of products; and a third storage area to store M/2 packed data elements, the third storage area corresponding to a N-bit destination specified by the first instruction to store the M/2 results; and a magnetic storage device to store said first instruction.

12. The computing system of claim 11 wherein N is 128.

13. The computing system of claim 12 wherein M is 16.

14. The computing system of claim 11 wherein N is 64.

15. The computing system of claim 14 wherein M is 8.

16. The computing system of claim 15 wherein said M packed data elements of the first storage area are treated as unsigned bytes.

17. The computing system of claim 16 wherein said M packed data elements of the second storage area are treated as signed bytes.

18. The computing system of claim 17 wherein each of said M/2 results are generated using signed saturation.