IP Library › Granted Patent US 7,395,375
Granted Patent B2
US 7,395,375 · App. 10/983,350 · Granted Jul 1, 2008

Prefetch miss indicator for cache coherence directory misses on external caches

Assignee: International Business Machines Corporation
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Quick Facts
Patent No.
US 7,395,375
App. No.
10/983,350
Granted
Jul 1, 2008
Kind
B2
Abstract

A system, method and article of manufacture for reducing latencies associated with cache coherence directory misses on external caches in a shared distributed memory data processing system. A cache coherence directory is evaluated for possible prefetching of a directory entry into a directory cache. A prefetch miss indicator is set if the prefetch evaluation results in a directory miss. The prefetch miss indicator is consulted during subsequent processing of a memory block request corresponding to the directory entry. An accelerated snoop response action is taken if the prefetch miss indicator is set. The latency of a second lookup into the cache coherence directory, which would otherwise be required, is thereby avoided.

Claims (14)

1. A method for reducing latency associated with cache coherence directory misses on external caches in a shared distributed memory data processing system, comprising:

evaluating a cache coherence directory for possible prefetching of a directory entry into a directory cache;

setting a prefetch miss indicator in response to said prefetch evaluation resulting in a directory miss;

consulting said prefetch miss indicator during subsequent processing of a memory request corresponding to said directory entry; and

taking an accelerated snoop response action without reevaluating said directory based on said prefetch miss indicator being set.

2. The method of claim 1 wherein said directory evaluating includes evaluating a full mapped directory.

3. The method of claim 1 wherein said directory evaluating includes evaluating a sparse directory.

4. The method of claim 1 wherein said setting of a prefetch miss indicator includes storing a tag for said directory entry.

5. The method of claim 1 wherein said setting of a prefetch miss indicator includes storing a tag for said directory entry in a prefetch miss buffer.

6. The method of claim 5 wherein said prefetch miss buffer comprises an addressable memory.

7. The method of claim 5 wherein said prefetch miss buffer comprises a storage register.

8. The method of claim 1 wherein said setting of a prefetch miss indicator includes setting a prefetch miss status indicator in said directory entry and storing said entry in said directory cache.

9. The method of claim 1 wherein said consulting of said prefetch miss indicator is performed by consulting a prefetch miss buffer in conjunction with consulting said directory cache.

10. The method of claim 1 wherein said consulting of said prefetch miss indicator is performed by consulting said directory cache to identify a directory entry having a prefetch miss status indicator.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 6, 2005
From: LAIS, ERIC N.; DESOTA, DONALD R.; JOERSZ, ROB
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 015549/0636 →
Continuity (1)
Related Publication 20060101209A1 · May 11, 2006