High-voltage tolerant power-rail ESD clamp circuit for mixed-voltage I/O interface
A circuit for electrostatic discharge (ESD) protection includes a resistor a capacitor connected in series with the resistor, a first transistor including a gate, the gate being connected to a first power supply providing a first voltage to the gate via the resistor and a first terminal connected to the first power supply, a second transistor including a gate, the gate being connected to a second power supply, the second power supply providing a second voltage smaller than the first voltage, the second transistor having a first terminal connected to a second terminal of the first transistor, and a third transistor including a gate, the gate being connected to the second power supply, a first terminal of the third transistor being connected to a second terminal of the second transistor, and a second terminal being connected to a reference voltage different from the first voltage and the second voltage.
1. A circuit for electrostatic discharge (ESD) protection, comprising:
a resistor;
a capacitor connected in series with the resistor;
a first transistor including a gate, the gate being connected to a first power supply providing a first voltage to the gate via the resistor and a first terminal connected to the first power supply;
a second transistor including a gate, the gate being connected to a second power supply, the second power supply providing a second voltage smaller than the first voltage, the second transistor having a first terminal connected to a second terminal of the first transistor;
a third transistor including a gate, the gate being connected to the second power supply, a first terminal of the third transistor being connected to a second terminal of the second transistor, and a second terminal being connected to a reference voltage different from the first voltage and the second voltage; and
a capacitor connected between the gate of the first transistor and the gate of the second transistor.
2. The circuit of claim 1 , further comprising a parasitic resistor formed between the second terminal of the second transistor and the reference voltage.
3. The circuit of claim 1 , further comprising a parasitic transistor including a base, the base being connected to the second terminal of the second transistor.
4. The circuit of claim 1 , wherein the second voltage is approximately half of the first voltage.
5. The circuit of claim 1 , further comprising a stacked n-type metal-oxide-semiconductor (“STNMOS”) device connected between the first power supply and the reference voltage.
6. The circuit of claim 1 , further comprising a silicon controlled rectifier (“SCR”) device connected between the first power supply and the reference voltage.
7. The circuit of claim 1 , further comprising a field oxide device (“FOD”) connected between the first power supply and the reference voltage.