Semiconductor memory
A semiconductor memory is achieved which allows a reduction in the area of a memory array block without reducing the gate widths of floating gates. A plurality of select gates extend in straight lines in the X direction. Between the upper- and lower-side select gates, two rows' worth of floating gates are arranged. The plurality of floating gates are placed in a staggered arrangement (in other words, in a zigzag pattern). That is, looking at one floating gate in a specific column and another floating gate in a column adjacent to that specific column, those floating gates deviate from each other in the Y direction.
1. A semiconductor memory comprising:
a select gate formed in a meandering pattern;
a plurality of floating gates coupled with said select gate, said plurality of floating gates including:
a first floating gate arranged to have its gate width defined along a first direction; and
a second floating gate arranged to be adjacent to said first floating gate and to have its gate width defined along a second direction perpendicular to said first direction;
a substrate having a major surface on which said select gate and said plurality of floating gates are formed respectively through gate insulating films;
a plurality of memory cells sharing said select gate and each having one of said plurality of floating gates; and
a potential supply circuit for supplying a potential to said plurality of memory cells,
wherein, for access to a memory cell selected from said plurality of memory cells, said potential supply circuit supplies to said selected memory cell a potential lower than a potential applied to said substrate.
2. The semiconductor memory according to claim 1 , further comprising:
a plurality of interconnect lines selectively serving as source or bit lines depending on a memory cell to be accessed.
3. The semiconductor memory according to claim 2 , wherein
said plurality of interconnect lines include:
a first interconnect line formed in a first interconnect layer; and
a second interconnect line formed adjacent to said first interconnect line in a second interconnect layer which is different from said first interconnect layer.