Circuit configuration having a feedback, fully-differential operational amplifier
The present invention relates to a circuit configuration having a feedback operational amplifier (AMP), which is implemented as fully differential, for amplifying an input signal differentially input to the circuit configuration and for outputting the amplified input signal as a differential output signal. In order to increase the freedom in setting the input common mode voltage, according to the present invention, a combination made of a coupling resistor (R 1 b ) and a level shifter (I 1 b , Nsfb) connecting the positive amplifier output (y 1 ) to the inverting amplifier input (x 2 ) and a combination made of a coupling resistor (R 1 a ) and a level shifter (I 1 a , Nsfa) connecting the negative amplifier output (y 2 ) to the noninverting amplifier input (x 1 ) are provided.
1. A circuit configuration having a circuit input (inp, inn) for an input signal to be amplified and a circuit output (outn, outp) for outputting the amplified input signal as an output signal,
the circuit configuration having a operational amplifier (AMP) implemented as fully-differential, having a noninverting amplifier input (x 1 ), an inverting amplifier input (x 2 ), a positive amplifier output (y 1 ) and a negative amplifier output (y 2 ),
the circuit input (inp, inn) being connected via coupling paths to the amplifier inputs (x 1 , x 2 ) and the amplifier outputs (y 1 , y 2 ) being connected via decoupling paths to the circuit output (outp, outn) and via feedback paths to the amplifier inputs (x 2 , x 1 ),
characterized by a combination made of a coupling resistor (R 1 b ) and a level shifter (I 1 b , Nsfb) connecting the positive amplifier output (y 1 ) to the inverting amplifier input (x 2 ) and a combination made of a coupling resistor (R 1 a ) and a level shifter (I 1 a , Nsfa) connecting the negative amplifier output (y 2 ) to the noninverting amplifier input (x 1 ).
2. The circuit configuration according to claim 1 , wherein at least a part of the coupling paths are formed by impedances having a capacitive component.
3. The circuit configuration according to claim 1 , wherein at least a part of the feedback paths are formed by impedances having a capacitive component.
4. The circuit configuration according to claim 1 , wherein the coupling resistors (R 1 a , R 1 b ) are each implemented as an ohmic resistor having a resistance value of more than 1 MΩ.
5. The circuit configuration according to claim 1 , wherein the two level shifters (I 1 a , Nsfa, I 1 b , Nsfb) each comprise a transistor (Nsfa, Nsfb) powered using a constant current source (I 1 a , I 1 b ).
6. The circuit configuration according to claim 5 , wherein the transistor (Nsfa, Nsfb) is an FET.
7. The circuit configuration according to claim 1 , wherein the two level shifters (I 1 a , Nsfa, I 1 b , Nsfb) are constructed identically.
8. The circuit configuration according to claim 1 , wherein the operational amplifier (AMP) has a setting input for setting the output common mode voltage (Vcm).
9. The circuit configuration according to claim 1 , wherein the operational amplifier (AMP) is connected to a first supply potential (GND) and a second supply potential (vdd) for its supply and the output common mode voltage (Vcm) is set as a predetermined fraction of the supply voltage (vdd-GND).
10. The circuit configuration according to claim 9 , wherein the fraction is in the range from 40% to 60%.
11. The circuit configuration according to claim 1 , wherein the operational amplifier (AMP) is connected to a first supply potential (GND) and a second supply potential (vdd) for its supply and the output common mode voltage (Vcm) is set as the supply voltage (vdd-GND) reduced by a predetermined reduction voltage.
12. The circuit configuration according to claim 11 , wherein the reduction voltage is in the range from 40 to 60% of a rated supply voltage (vdd-GND) of the operational amplifier (AMP).
13. The circuit configuration according to claim 1 , wherein the coupling paths for changing a circuit amplification each comprise impedances (C 3 a , C 3 b ) which are each connectable and disconnectable via a transistor (Nsa, Nsb).