Systems and methods for enhancing performance of a coprocessor
Techniques for minimizing coprocessor “starvation,” and for effectively scheduling processing in a coprocessor for greater efficiency and power. A run list is provided allowing a coprocessor to switch from one task to the next, without waiting for CPU intervention. A method called “surface faulting” allows a coprocessor to fault at the beginning of a large task rather than somewhere in the middle of the task. DMA control instructions, namely a “fence,” a “trap” and a “enable/disable context switching,” can be inserted into a processing stream to cause a coprocessor to perform tasks that enhance coprocessor efficiency and power. These instructions can also be used to build high-level synchronization objects. Finally, a “flip” technique is described that can switch a base reference for a display from one location to another, thereby changing the entire display surface.
1. A method for streamlining operations in a coprocessor by ensuring all required memory resources for a task are available, comprising:
prior to beginning the processing of the task,
preparing the task for processing in a coprocessor by paging memory resources, within a memory space accessible by the coprocessor, associated with the task into coprocessor-readable memory;
sampling the memory resources to determine if all required memory resources are in a proper location in the coprocessor-readable memory; and
recording whether all required memory resources are in a proper location in the coprocessor-readable memory, wherein said recording generates an indicator memory resource that is associated with the task;
processing said indicator memory resource substantially at the beginning of processing the task, wherein when said indicator memory resource indicates that all required memory resources are not in the proper location in the coprocessor-readable memory, a first page fault is generated, and the coprocessor stops beginning the processing of the task, wherein a list of tasks is maintained that comprises tasks that the coprocessor stopped processing; and
generating a second page fault when a context switch occurs to a task that references an invalid ring buffer or an invalid DMA buffer.
2. A method according to claim 1 wherein the coprocessor is a Graphics Processing Unit (GPU).
3. A method according to claim 1 wherein the task is represented by a DMA buffer.
4. A method according to claim 1 , further comprising utilizing said list to bring required memory resources to a proper location in coprocessor-readable memory at a later time.
5. A method according to claim 4 wherein the later time is determined based on a priority of tasks on the list of tasks.
6. A method according to claim 5 , further comprising a periodic priority boost that increases the priority of one or more tasks on the list of tasks to ensure that all tasks eventually can be processed.
7. A method for streamlining operations in a coprocessor by ensuring all required memory resources for a task are available, comprising:
prior to beginning the processing of the task,
preparing the task for processing in a Graphics Processing Unit (GPU) by paging memory resources within a memory space accessible by the GPU associated with the task into GPU readable memory;
sampling the memory resources to determine if all required memory resources are in a proper location in the GPU readable memory; and
recording whether all required memory resources are in a proper location in the GPU readable memory, wherein said recording generates an indicator memory resource that is associated with the task;
processing said indicator memory resource prior to beginning processing the task, wherein when said indicator memory resource indicates that all required memory resources are not in the proper location in the GPU readable memory, a first page fault is generated, the task is not processed and wherein a list of tasks is maintained that comprises tasks that the coprocessor stopped processing; and
generating a second page fault when a context switch occurs to a task that references an invalid ring buffer or an invalid DMA buffer.
8. A method according to claim 7 wherein the task is represented by a DMA buffer.
9. A method according to claim 7 wherein the later time is determined based on a priority of tasks on the list of tasks.
10. A method according to claim 9 , further comprising a periodic priority boost that increases the priority of one or more tasks on the list of tasks to ensure that all tasks eventually can be processed.