Static random access memory device having a high-bandwidth and occupying a small area
An SRAM device is disclosed, which comprises a plurality of rows of SRAM cells and a line-buffer SRAM cell. Each row of SRAM cells is controlled by a word line. The line-buffer SRAM cell is coupled to the rows of SRAM cells and controlled by a read enable line. The signal on the read enable line is activated after the signal on the word line is activated, and part of the activated signal on the read enable line overlaps with the activated signal on the word line. The power provided to the line-buffer SRAM cell is selectively cut off.
1. An SRAM device having two outputs respectively coupled to two different apparatuses outside the SRAM device, comprising:
a plurality of rows of SRAM cells, each row being connected to one of a plurality of word lines and a plurality of bit lines;
a decoder coupled between said plurality of rows of SRAM cells and one of the two outputs, and connected to the bit lines for accessing one of the bit lines; and
a row of line-buffer SRAM cells, coupled between said plurality of rows of SRAM cells and the other one of the two outputs, being connected to a read enable line and the bit lines, wherein said row of line-buffer SRAM cells is configured to allow data stored within one of said plurality of rows of SRAM cells to be duplicated to said row of line-buffer SRAM cells, wherein the plurality of rows of SRAM cells and the row of line-buffer SRAM cells form a SRAM cell array;
wherein a signal on said read enable line is activated after a signal on said one of the plurality of word lines is activated, and p art of a duration of the activated signal on said read enable line overlaps with part of a duration of the activated signal on said one of the plurality of word lines.
2. The SRAM device of claim 1 , wherein power provided to said row of line-buffer SRAM cells is selectively cut off.
3. An SRAM device having two outputs respectively coupled to two apparatuses outside the SRAM device, comprising:
an SRAM cell array comprising at least one row of SRAM cells and at least one column of SRAM cells;
a X-decoder, wherein said X-decoder is connected to said SRAM cell array;
a Y-decoder, wherein said Y-decoder is connected between said SRAM cell array and one of the two outputs; and
a row of SRAM cells in said SRAM cell array, coupled between said SRAM cell array and the other one of the two outputs, and connected to a read enable line, said row of SRAM cells configured to store data duplicated from a row of SRAM cells in the SRAM cell array.
4. The SRAM device of claim 3 , further comprising a sense amplifier which is connected to said Y-decoder.
5. The SRAM device of claim 4 , wherein said sense amplifier is connected to a micro-controller.
6. The SRAM device of claim 3 , wherein said row of SRAM cells functions as a line-buffer.
7. The SRAM device of claim 3 , wherein the SRAM device further comprises a plurality of word lines coupled to the SRAM cell array, and a signal on said read enable line is activated after a signal on one of the word lines is activated, and part of a duration of the activated signal on said read enable line overlaps with part of a duration of the activated signal on said one of the word lines.
8. The SRAM device of claim 3 , wherein the other one of the two outputs is coupled to a LCD source.
9. The SRAM device of claim 3 , wherein the Y-decoder is coupled between one side of said plurality of rows of SRAM cells and one of the two outputs, and the row of SRAM cells is coupled between the other side of said plurality of rows of SRAM cells and the other one of the two outputs.
10. The SRAM device of claim 1 , wherein the decoder is coupled between one side of said plurality of rows of SRAM cells and one of the two outputs, and the row of line-buffer SRAM cells is coupled between the other side of said plurality of rows of SRAM cells and the other one of the two outputs.