Method to reduce transient current swings during mode transitions of high frequency/high power chips
View Patent ↗A method, an apparatus, and a computer program are provided to reduce transient current swings during mode transitions. Traditionally, transient supply voltage fluctuations on a chip account for a large portion of the power supply. The number of series inductances and resistances are typically minimized, while adding large decoupling capacitances between the supply voltage and ground. However, situations may arise where reduction of series inductances and resistances cannot be accomplished. Therefore, to assist in controlling the transient current swings, reduction of clocking frequencies are performed in a controlled manner.
1. A method for reducing transient current swings during mode transitions of high frequency/high power circuits, comprising:
providing a high frequency clocking signal; and
reducing the frequency over a plurality of pulses to control rate of change of current consumption from a power supply, wherein reducing the frequency over a plurality of pulses comprises:
generating, by a finite state machine, an n-bit shift register input and a load signal;
receiving, by an n-bit ring shift register divider, the load signal and the n-bit shift register input;
responsive to the load signal being asserted generating, by the n-bit ring shift register divider, a register output;
receiving the load signal, the high frequency clocking signal, and the register output at a logic module;
masking, by the logic module, the high frequency clocking signal according to the register output to generate a divided clock signal and
selecting, by the logic module, between the high frequency clocking signal and the divided clock signal based on the load signal.
2. The method of claim 1 , wherein reducing the frequency further comprises reducing the high frequency clocking signal over a plurality of stages.
3. The method of claim 2 , wherein one stage of the plurality of stages comprises dropping at least one pulse out of a plurality of consecutive pulses.
4. The method of claim 2 , wherein one stage of the plurality of stages comprises dropping more than one pulse out of a plurality of consecutive pulses.
5. The method of claim 1 , further comprising shifting, by the n-bit ring shift register divider, bits in a loop controlled by the high frequency clocking signal.
6. The method of claim 1 , wherein masking the high frequency clocking signal comprises:
receiving, by a logic gate the register output of the n-bit ring shift register divider and the high frequency clocking signal; and
performing a logic operation on the register output and the high frequency clocking signal to generate the divided clock signal.
7. The method of claim 6 , wherein the logic operation is a logic AND operation.
8. The method of claim 6 , wherein selecting between the high frequency clocking signal and the divided clock signal based on the load signal comprises:
receiving, at selective logic, an output of the logic gate and an output of the high frequency signal source; and
selecting, by the selective logic, between the high frequency clock signal and the divided clock signal.
9. The method of claim 6 , wherein the selective logic is configured to select the high frequency clock signal when the load signal is not asserted.
10. The method of claim 6 , wherein the selective logic is configured to select the divided clock signal when the load signal is asserted.