Method and apparatus to control a power consumption of a memory device
In one embodiment, a method is provided. The method comprises upon entering a self-refresh mode, refreshing memory cells in a memory device at a first refresh frequency; and upon a predefined event refreshing the memory cells at a second refresh frequency, while in the self-refresh mode.
1. An apparatus comprising:
a memory array including a plurality of memory cells;
a temperature sensing device coupled to the memory array for monitoring the temperature associated with the memory array; and
logic, coupled to the memory array, configured to dynamically change a refresh frequency at which the memory cells are refreshed during a self refresh mode, wherein the change in the refresh frequency depends on whether the temperature associated with the memory array has exceeded a threshold temperature, wherein the temperature sensing device includes a first transistor and the temperature monitoring of the memory array is done by using charge accumulation on the first transistor.
2. The apparatus of claim 1 wherein the temperature sensing device is a thermal sensor.
3. The apparatus of claim 1 wherein the plurality of memory cells are DRAM cells.
4. The apparatus of claim 1 wherein the temperature sensing device and the memory array with the plurality of memory cells are on a same die.
5. The apparatus of claim 1 wherein the logic has an algorithm that automatically doubles the refresh frequency if the temperature of the memory array exceeds the threshold temperature.
6. An apparatus comprising:
a memory module Including
a memory array including a plurality of volatile memory cells;
a temperature sensing device attached to the memory array for monitoring the temperature associated with the memory array; and
logic, coupled to the memory array, configured to dynamically change a refresh frequency at which the volatile memory cells are refreshed during a self refresh mode, wherein the change in the refresh frequency depends on whether or not the temperature associated with the memory array has exceeded a threshold temperature, wherein the temperature sensing device includes a single transistor and the temperature monitoring of the memory array is done by using charge accumulation on the single transistor.
7. The apparatus of claim 6 wherein the temperature sensing device is a thermal sensor.
8. The apparatus of claim 7 wherein the plurality of volatile memory cells are a DRAM cells.
9. The apparatus of claim 6 wherein the temperature sensing device and the memory array with the plurality of volatile memory cells are on a same die within the memory module.
10. The apparatus of claim 6 wherein the logic has an algorithm that doubles the refresh frequency if the temperature of the memory array exceeds the threshold temperature.
11. A method comprising:
coupling a temperature sensing device to a memory array including a plurality of volatile memory cells;
monitoring a temperature associated with a memory array that includes a plurality of volatile memory cells;
monitoring the temperature associated with the memory array through charge accumulation on a transistor based device; and
dynamically changing a refresh frequency at which the volatile memory cells are refreshed during a self refresh mode, wherein the change in the refresh frequency depends on a detected temperature associated with the memory array and a threshold temperature value.
12. The method of claim 11 , further comprising:
at least doubling the refresh frequency if the temperature of the memory array exceeds the threshold temperature.
13. A system, comprising:
a memory module comprising
at least one memory device, the memory device including a memory array comprising volatile memory cells;
a temperature sensing device attached to the memory array for detecting the temperature associated with the memory array; and
logic, coupled to the memory array, configured to change a refresh frequency at which the volatile memory cells are refreshed during a self refresh mode, wherein the change in the refresh frequency depends on at least whether the temperature associated with the memory array has exceeded a threshold temperature;
a memory controller coupled to the memory module; and
a network interface associated with the memory module to allow the system to communicate with a network, wherein the temperature sensing device includes a first transistor and the temperature monitoring of the memory array is done by using charge accumulation on the first transistor.
14. The system of claim 13 wherein the temperature sensing device is a thermal sensor and the volatile memory cells are DRAM cells.
15. The system of claim 14 wherein the temperature sensing device and the memory array with a plurality of DRAM cells are on the same die.
16. The system of claim 13 wherein the logic has an algorithm that at least doubles the refresh frequency if the temperature of the memory array exceeds the threshold temperature.