IP Library › Granted Patent US 7,436,752
Granted Patent B2
US 7,436,752 · App. 11/164,320 · Granted Oct 14, 2008

Method and apparatus for signal equalization in a light storage system

Assignee: Realtek Semiconductor Corp.
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Quick Facts
Patent No.
US 7,436,752
App. No.
11/164,320
Granted
Oct 14, 2008
Kind
B2
Abstract

A method and apparatus for signal equalization in a light storage system is disclosed. The method includes observing run length of an RF signal read from the optical disc; classifying run lengths into sets; calculating the mean of certain run lengths; comparing the values with expected values of said run lengths to generate an error value; and adjusting equalizing parameters of boost and frequency if the error value lies outside an expected range.

Claims (37)

1. A method for signal equalization in a light storage system, the method comprising:

measuring a plurality of run lengths of a signal;

classifying measured run lengths into a plurality of run length sets;

calculating a first average value of a first run length set corresponding to a first run length;

calculating a second average value of a second run length set corresponding to a second run length;

comparing the first average value with a first expected value of the first run length set to determine a first difference value;

comparing the second average value with a second expected value of the second run length set to determine a second difference value; and

adjusting a first parameter to reduce the first difference value and adjusting a second parameter to reduce the second difference value until the first difference value falls within a first range and the second difference value falls within a second range.

2. The method of claim 1 wherein the first parameter is to set boost applied to equalizing the signal.

3. The method of claim 2 wherein the second parameter is a central frequency.

4. The method of claim 1 wherein the first expected value is equal to the first run length, and the second expected value is equal to the second run length.

5. The method of claim 4 wherein the first run length is 3T run length, and the second run length is 4T run length.

6. The method of claim 1 wherein the step of adjusting the first and second parameters further comprises:

if the first difference value is above the first range, decreasing the first parameter;

if the first difference value is below the first range, increasing the first parameter;

if the second difference value is above the second range, decreasing the second parameter; and

if the second difference value is below the second range, increasing the second parameter.

7. The method of claim 1 wherein the step of adjusting the first parameter and the step of adjusting the second parameter are performed alternately.

8. The method of claim 6 wherein the step of adjusting the first and second parameters is performed by applying a predetermined step size.

9. An apparatus for signal equalization in a light storage system, the apparatus comprising:

a run length meter comprising:

a measuring module for measuring a plurality of run lengths of the signal;

a classifying module coupled to the measuring module for classifying measured run lengths into a plurality of run length sets;

a calculating module coupled to the classifying module for calculating a first average value of a first run length set corresponding to a first run length and for calculating a second average value of a second run length set corresponding to a second run length; and

a comparing module, coupled to the calculating module, for comparing the first average value with a first expected value of the first run length set to determine a first difference value and for comparing the second average value with a second expected value of the second run length set to determine a second difference value; and

a processor, coupled to an equalizer and the run length meter, for adjusting a first parameter to reduce the first difference value and adjusting a second parameter to reduce the second difference value until the first difference value falls within a first range and the second difference value falls within a second range.

10. The apparatus of claim 9 wherein the first parameter is to set boost.

11. The apparatus of claim 10 wherein the second parameter is a central frequency.

12. The apparatus of claim 9 wherein the first expected value is equal to the first run length, and the second expected value is equal to the second run length.

13. The apparatus of claim 12 wherein the first run length is 3T run length, and the second run length is 4T run length.

14. The apparatus of claim 9 wherein the processor adjusts the first and second equalizing parameters by:

if the first difference value is above the first range, decreasing the first equalizing parameter;

if the first difference value is below the first range, increasing the first equalizing parameter;

if the second difference value is above the second range, decreasing the second equalizing parameter; and

if the second difference value is below the second range, increasing the second equalizing parameter.

15. The apparatus of claim 9 wherein the processor alternately adjusts the first parameter and the second parameter.

16. The apparatus of claim 15 wherein the processor adjusts the parameters by applying a predetermined step size.

Assignments (2)
CHANGE OF THE ADDRESS OF THE ASSIGNEE Recorded Sep 4, 2008
From: REALTEK SEMICONDUCTOR CORP.
To: REALTEK SEMICONDUCTOR CORP.
Reel/Frame 021477/0570 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 17, 2005
From: HE, WEI-HUNG
To: REALTEK SEMICONDUCTOR CORP.
Reel/Frame 016795/0873 →
Continuity (1)
Related Publication 20070109950A1 · May 17, 2007