Highly compact non-volatile memory and method therefor with internal serial buses
A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. Redundant circuits among each stack are factored out. In one aspect, a serial bus allows communication between components in each stack, thereby reducing the number of connections in a stack to a minimum. A bus controller sends control and timing signals to control the operation of the components and their interactions through the serial bus. In a preferred embodiment, the bus transactions of corresponding components in all the similar stacks are controlled simultaneously.
1. A non-volatile memory device, comprising:
an array of memory cells;
a set of sensing circuits for operating on a set of memory cells in parallel among said array;
said set of sensing circuits having a plurality of components;
said plurality of component further comprising core portions of corresponding sensing circuits of the set and a common portion shared by the set;
said plurality of components being organized into a bank of stacks, each stack serving a segment of the set of memory cells in parallel;
a stack bus for each stack coupling between individual components therein; and
a stack bus controller coupled to said individual components to control operations of said individual components with said stack bus.
2. A non-volatile memory device as in claim 1 , wherein:
data is exchanged between said individual components; and
said stack bus is a serial bus that transfers the data serially.
3. A non-volatile memory device as in claim 1 , wherein:
individual stacks in the bank are substantially similar to each other; and
said memory device further comprising:
one or more control lines connecting said stack bus controller simultaneously to corresponding components among the stacks in the bank.
4. A non-volatile memory device as in claim 1 , wherein:
said stack bus is further segmented into a first and second segments;
said first segment is coupled to a first group of individual components among each stack;
said second segment is coupled to a second group of individual components among each stack; and
at least one of the individual components is common to said first and second groups.
5. A non-volatile memory device as in any one of claims 1 - 4 , wherein said array of memory cells is constituted from flash EEPROM cells.
6. A non-volatile memory device as in any one of claims 1 - 4 , wherein said array of memory cells is constituted from NROM cells.
7. A non-volatile memory device, as in any one of claims 1 - 4 , wherein each memory cell stores one bit of data.
8. A non-volatile memory device as in any one of claims 1 - 4 , wherein each memory cell stores more than one bit of data.
9. A method of reducing the number of connections between a set of sensing circuits in an array of non-volatile memory cells, comprising:
partitioning the set of sensing circuits into a plurality of components, said plurality of components further comprising core portions of corresponding sensing circuits of the set and a common portion shared by the set;
organizing the set of sensing circuits into a bank of stacks, each stack containing individual components similar to other stacks in the bank;
coupling the individual components of each stack by a bus; and
controlling operations of the individual components of each stack and its bus by sending control signals to individual components of each stack.
10. The method as in claim 9 , further including:
exchanging data between said individual components; and
transferring data serially between the individual components by said stack bus.
11. The method as in claim 9 , further including:
sending said control signals simultaneously to similar individual components of all stacks in the bank.
12. The method as in claim 9 , further including:
segmenting said bus into first and second segments;
coupling said first segment to a first group of individual components among each stack; and
coupling said second segment to a second group of individual components among each stack,
wherein at least one of the individual components is common to said first and second groups.
13. The method as in any one of claims 9 - 12 , wherein said array of memory cells is constituted from flash EEPROM cells.
14. The method as in any one of claims 9 - 12 , wherein said array of memory cells is constituted from NROM cells.
15. The method as in any one of claims 9 - 12 , wherein each memory cell stores one bit of data.
16. The method as in any one of claims 9 - 12 , wherein each memory cell stores more than one bit of data.