Dynamic random access memories and method for testing performance of the same
View Patent ↗The present invention enables screening of the so-called variable retention time (VRT) failure, namely a retention failure occurring in a DRAM due to fluctuation of a data retention time like a random telegraph noise. A pause/refresh test for checking a data retention function is repeated at all memory cells of a chip so that memory cells at which the retention failure due to random fluctuation of the data retention capability over time may occur is subjected to screening.
1. A method of checking a dynamic random access memory with a plurality of memory cell each having a data retention capability incorporated therein, comprising:
a step of repeatedly executing a pause/refresh test for checking the memory cells for the data retention function several times under the substantially same testing conditions, thereby screening a retention failure caused by a random fluctuation in a data retention capability of the memory cell over time, and
a step of applying a bias higher than a voltage applied for operations of the dynamic random access memory to a PN junction between a diffused layer of a storage node constituting the memory cell and a substrate in the reverse direction in repetition of the pause/refresh test before the pause/refresh operation is started.
2. The method of checking a dynamic random access memory according to claim 1 ,
wherein the pause/refresh test for checking the memory cells for the data retention function is repeated up to N times decided according to a prespecified screening rate.
3. The method of checking a dynamic random access memory according to claim 1 ,
wherein the pause/refresh test is repeated at a temperature higher than an operating temperature for use of the dynamic random access memory.
4. The method of checking a dynamic random access memory according to claim 1 , further comprising:
a step of applying, in repetition of the pause/refresh test, a reverse bias higher than a voltage applied for operations of the dynamic random access memory to a PN junction between a diffused layer of a storage node constituting the memory cell and a substrate before start of the pause/refresh operation, and then carrying out the pause/refresh test at an atmosphere in temperature higher than the operating temperature for use of the dynamic random access memory.
5. The method of checking a dynamic random access memory according to claim 1 , further comprising:
a step of stopping application of a voltage to all terminals of the memory cell, in repetition of the pause/refresh test, before start of the pause/refresh operation.
6. The method of checking a dynamic random access memory according to claim 1 , further comprising:
a step of stopping application of a voltage to all terminals of the memory cell, in repetition of the pause/refresh test, before start of the pause/refresh operation, and then carrying out the pause/refresh test at an atmosphere in temperature higher than the operating temperature for use of the dynamic random access memory.
7. The method of checking a dynamic random access memory according to claim 1 , further comprising:
a step of stopping application of a voltage to all terminals of the memory cell, in repetition of the pause/refresh test, before start of the pause/refresh operation; and
a step of applying a reverse bias higher than a voltage applied for operations of the dynamic random access memory to a PN junction between a diffused layer on a storage node constituting the memory cell and a substrate,
wherein each of the steps is repeatedly executed up to N times.
8. The method of checking a dynamic random access memory according to claim 1 , further comprising:
a step of repeating a write operation and a pause operation of the memory cell several times while applying a reverse bias higher than a voltage applied for operation of the dynamic random access memory to a PN junction between a diffused layer on a storage node constituting the memory cell and a substrate.
9. A method of checking a dynamic random access memory with a plurality of memory cell each having a data retention capability incorporated therein, comprising:
a step of repeatedly executing a pause/refresh test for checking the memory cells for the data retention function several times under the substantially same testing conditions, thereby screening a retention failure caused by a random fluctuation in a data retention capability of the memory cell over time, and
a step of applying a forward bias to a PN junction between a diffused layer on a storage node constituting the memory cell and a substrate, in repetition of the pause/refresh test, before start of the pause/refresh operation.
10. The method of checking a dynamic random access memory according to claim 9 , further comprising:
a step of applying a forward bias to a PN junction between a diffused layer on a storage node constituting the memory cell and a substrate, in repetition of the pause/refresh test, before start of the pause/refresh operation, and then carrying out the pause/refresh test at an atmosphere in a temperature higher than the operating temperature for use of the dynamic random access memory.
11. The method of checking a dynamic random access memory according to claim 9 , further comprising:
a step of applying a forward bias to a PN junction between a diffused layer on a storage node constituting the memory cell and a substrate, in repetition of the pause/refresh test, before start of the pause/refresh operation; and
a step of applying a reverse bias higher than a voltage applied for operations of the dynamic random access memory to a PN junction between a diffused layer on a storage node constituting the memory cell and a substrate;
wherein each of the steps is repeatedly executed up to N times.
12. A method of checking a dynamic random access memory with a plurality of memory cell each having a data retention capability incorporated therein, comprising:
a step of repeating a write operation of the memory cell several times under the bias condition generating hot carriers more than those generated during a write operation when the dynamic random access memory is running, and then,
a step of repeatedly executing a pause/refresh test for checking the memory cells for the data retention function several times under the substantially same testing conditions, thereby screening a retention failure caused by a random fluctuation in a data retention capability of the memory cell over time.
13. A dynamic random access memory comprising:
a pause/refresh test circuit for executing, in a dynamic random access memory having a plurality of memory cells each having a data retention function, a pause/refresh test for checking the memory cells for the data retention function;
a reverse bias test circuit for generating a reverse bias higher than a voltage applied for operation of the dynamic random access memory to a PN junction between a diffused layer on a storage node constituting the memory cell and a substrate; and
a switch circuit for switching between the pause/refresh test circuit and the reverse bias test circuit.
14. The dynamic random access memory according to claim 13 ,
wherein a forward bias test circuit for generating a forward bias different from the forward bias applied for operation of the dynamic random access memory to a PN junction between a diffused layer on a storage node constituting the memory cell and a substrate is provided in place of the reverse bias test circuit.
15. A dynamic random access memory comprising:
a test circuit for applying to the word line a voltage lower than a voltage applied to a word line in a write operation when the dynamic random access memory is running but higher than a voltage applied to the word line in a pause operation;
a test circuit for applying to the bit line a voltage higher than a voltage applied to a bit line in a write operation when the dynamic random access memory is running; and
a switch circuit for switching between the two circuits and a normal operation circuit of the dynamic random access memory.