High performance system-on-chip using post passivation process
The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.
1. A chip comprising:
a silicon substrate;
a transistor in or on said silicon substrate;
a metallization structure over said silicon substrate, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer;
a dielectric layer between said first and second metal layers;
a pad over said silicon substrate, wherein said pad has a top surface with a first region and a second region surrounding said first region;
a passivation layer over said metallization structure and over said dielectric layer, wherein said passivation layer is on said second region, and an opening in said passivation layer is over said first region, wherein said opening exposes said first region, wherein said opening has a width smaller than that of said pad, and wherein said opening has a transverse dimension between 0.5 and 30 micrometers, and wherein said passivation layer comprises a nitride layer;
a polymer layer over said passivation layer, wherein said polymer layer has a thickness greater than that of said passivation layer and between 2.0 and 150 μm;
a gold coil over said polymer layer, wherein said gold coil comprises an electroplated gold layer having a thickness greater than that of said pad, and wherein said gold coil is connected to said pad through said opening; and
a third metal layer between said passivation layer and said polymer layer and under said gold coil.
2. The chip of claim 1 , wherein said third metal layer comprises a gold layer between said passivation layer and said polymer layer and under said gold coil.
3. The chip of claim 1 , wherein said third metal layer comprises a copper layer between said passivation layer and said polymer layer and under said gold coil.
4. The chip of claim 1 , wherein said polymer layer comprises polyimide.
5. The chip of claim 1 , wherein said passivation layer further comprises an oxide layer under said nitride layer.
6. The chip of claim 5 , wherein said oxide layer has a thickness between 0.15 and 2.0 micrometers.
7. The chip of claim 1 , wherein said nitride layer has a thickness between 0.5 and 2.0 micrometers.
8. The chip of claim 1 , wherein said polymer layer comprises benzocyclobutene (BCB).
9. The chip of claim 1 , wherein said pad comprises electroplated copper.
10. The chip of claim 1 , wherein said pad comprises aluminum.
11. The chip of claim 1 , wherein said third metal layer comprises an aluminum layer between said passivation layer and said polymer layer and under said gold coil.
12. The chip of claim 1 , wherein said third metal layer comprises a layer of ferromagnetic material between said passivation layer and said polymer layer and under said gold coil.
13. The chip of claim 1 further comprising electroplated copper in said opening, over said pad and under said gold coil.
14. The chip of claim 1 further comprising nickel over said pad and under said gold coil.