Programmable state machine of an integrated circuit
A programmable state machine of an application specific integrated circuit (ASIC) is programmed by enabling the scan mode of the integrated circuit. The process of programming the state machine continues by loading, through at least one scan chain to which the state machine is coupled, at least one timing sequence instruction into scan capable registers of the state machine. Once the at least one timing sequence instruction has been loaded into the scan capable registers, the scan mode is disabled and normal mode of the integrated circuit is resumed.
1. A method for programming a state machine of an integrated circuit, the method comprises:
enabling scan mode of a scan/normal mode state for the integrated circuit, wherein the state machine is operably coupled to at least one scan chain;
loading, through the at least one scan chain, at least one timing sequence instruction into scan capable registers of the state machine;
enabling normal mode of the scan/normal mode state when the at least one timing sequence instruction has been loaded;
in the normal mode, generating, by the state machine, a data control signal based on the at least one timing seciuence instruction; and
in the normal mode, providing, by the state machine, the data control signal to a digital circuit module that converts a digital input into a digital output based on the data control signal.
2. The method of claim 1 further comprises reprogramming the state machine by:
enabling the scan mode;
overwriting, via the at least one scan chain, the at least one timing sequencer instruction with at least one new timing sequence instruction; and
disabling the scan mode when the at least one timing sequence instruction has been overwritten.
3. The method of claim 1 further comprises:
enabling the scan mode of the scan/normal mode state, wherein a plurality of state machines is operably coupled to the at least one scan chain of the integrated circuit, wherein the plurality of state machines includes the state machine;
loading, through the at least one scan chain, a plurality of timing sequence instructions into scan capable registers of corresponding ones of the plurality of state machines, wherein the plurality of timing sequence instructions includes the at least one timing sequence instruction;
enabling the normal mode of the scan/normal mode state when the plurality of timing sequence instructions has been loaded;
in the normal mode, generating, by the plurality of state machines, a plurality of data control signals based on the plurality of timing sequence instructions; and
in the normal mode, providing, by the plurality of state machines, the plurality of data control signals to a plurality of digital circuit modules, wherein the plurality of data control signals includes the data control signal and the plurality of digital circuit modules includes the digital circuit module.
4. The method of claim 1 , wherein the loading of the at least one timing sequence instruction further comprises serially loading the at least one timing sequence instruction through the at least one scan chain.
5. The method of claim 1 , wherein the loading of the at least one timing sequence instruction further comprises:
reading the at least one timing sequence instruction from memory.
6. The method of claim 1 , wherein the scan capable registers of the state machine further comprise scan enabled flip-flops.
7. The method of claim 1 , wherein the loading of the at least one timing sequence instruction further comprises:
receiving the at least one timing sequence instruction from a processor via a serial port of the integrated circuit.
8. The method of claim 1 , wherein the at least one timing sequence instruction comprises at least one of an initial count value field, a next address field, a conditional jump field, a load counter field, a count enable field, and control signals.
9. A programmable state machine of an integrated circuit comprises:
processing module; and
memory operably coupled to the processing module, wherein the memory stores operational instructions that cause the processing module to:
enable scan mode of a scan/normal mode state of the integrated circuit, wherein the state machine is operably coupled to at least one scan chain;
load, through the at least one scan chain, at least one timing sequence instruction into scan capable registers of the state machine; and
enable normal mode of the scan/normal mode state when the at least one timing sequence instruction has been loaded, wherein, in the normal mode, the state machine generates a data control signal based on the at least one timing sequence instruction and provides the data control signal to a digital circuit module.
10. The programmable state machine of claim 9 , wherein the memory further comprises operational instructions that cause the processing module to reprogram the state machine by:
enabling the scan mode;
overwriting, via the at least one scan chain, the at least one timing sequencer instruction with at least one new timing sequence instruction; and
disabling the scan mode when the at least one timing sequence instruction has been overwritten.
11. The programmable state machine of claim 9 , wherein the memory further comprises operational instructions that cause the processing module to:
enable scan mode of the scan/normal mode state, wherein a plurality of state machines is operably coupled to the at least one scan chain of the integrated circuit, wherein the plurality of state machines includes the state machine;
load, through the at least one scan chain, a plurality of timing sequence instructions into scan capable registers of corresponding ones of the plurality of state machines, wherein the plurality of timing sequence instructions includes the at least one timing sequence instruction; and
enable the normal mode of the scan/normal mode state when the plurality of timing sequence instructions has been loaded, wherein, in the normal mode, the plurality of state machines generate a plurality of data control signals based on the plurality of timing sequence instructions and provide the plurality of data control signals to a plurality of digital circuit modules, wherein the plurality of data control signals includes the data control signal and the plurality of digital circuit modules includes the digital circuit module.
12. The programmable state machine of claim 9 , wherein the memory further comprises operational instructions that cause the processing module to load the at least one timing sequence instruction by serially loading the at least one timing sequence instruction through the at least one scan chain.
13. The programmable state machine of claim 9 , wherein the memory further comprises operational instructions that cause the processing module to load the at least one timing sequence instruction by:
reading the at least one timing sequence instruction from memory.
14. The programmable state machine of claim 9 , wherein the scan capable registers of the state machine further comprise scan enabled flip-flops.
15. The programmable state machine of claim 9 , wherein the memory further comprises operational instructions that cause the processing module to load the at least one timing sequence instruction by:
receiving the at least one timing sequence instruction from a processor via a serial port of the integrated circuit.
16. The programmable state machine of claim 9 , wherein the at least one timing sequence instruction comprises an initial count value field, a next address field, a conditional jump field, a load counter field, a count enable field, and control signals.
17. An on-chip programmable circuit comprises:
at least one instruction register, wherein each of the at least one instruction registers includes:
a plurality of scan enabled flip-flops operably coupled to:
store at least one timing sequence instruction from at least one scan chain when the on-chip programmable circuit is in a scan mode, the at least one timing sequence instruction is written into the plurality of scan enabled flip-flops; and
provide the at least one timing sequence instruction when the on-chip programmable circuit is in a normal mode; and
state machine logic circuitry operably coupled to process the at least one timing sequence instruction to produce at least one control signal when the on-chip programmable circuit is normal mode; and
a digital circuit module coupled to convert input data into output data based on the at least one control signal when the on-chip programmable circuit is the normal mode.
18. The on-chip programmable circuit of claim 17 further comprises:
a plurality of reserved scan enabled flip-flops operably coupled to the scan chain and is operably coupled to store at least one additional timing sequence instruction when the on-chip programmable circuit is reprogrammed.
19. The on-chip programmable circuit of claim 17 , wherein the at least one instruction register further comprises a plurality of instruction registers, wherein each of the plurality of instruction registers stores a corresponding timing sequence instruction of a state machine algorithm.
20. The on-chip programmable circuit of claim 19 , wherein the state machine logic circuitry further comprises:
an address generator operably coupled to address one of the plurality of instruction registers based on at least one of an external event and the corresponding timing sequence instruction of the one of the plurality of instruction registers or another one of the plurality of instruction registers.
21. The on-chip programmable circuit of claim 17 , wherein the at least one timing sequence instruction comprises an initial count value field, a next address field, a conditional jump field, a load counter field, a count enable field, and control signals.
22. The on-chip programmable circuit of claim 17 , wherein the plurality of scan enabled flip-flops is daisy chained together to serially receive and store the at least one timing sequence instruction.
23. A programmable application specific integrated circuit (ASIC) comprises:
plurality of data flow control state machines, wherein each of the plurality of data flow control state machines generates at least one control signal and includes:
at least one instruction register, wherein each of the at least one instruction registers includes:
a plurality of scan enabled flip-flops operably coupled to:
store at least one timing sequence instruction when the programmable ASIC is in a scan mode, the at least one timing sequence instruction is written into the plurality of scan enabled flip-flops; and
provide the at least one timing sequence instruction when the programmable ASIC is in a normal mode;
state machine logic circuitry operably coupled to process the at least one timing sequence instruction to produce the at least one control signal when the the programmable ASIC is in the normal mode;
plurality of digital circuit modules, each of the plurality of digital circuit modules operably coupled to process data based on the at least one control signal of a corresponding one of the plurality of data flow control state machines; and
control module operably coupled to establish the scan mode and the normal mode based on a mode select input.
24. The programmable ASIC of claim 23 further comprises:
an input select port operably coupled to receive the mode select input, wherein the mode select input is one of: program mode, scan mode, reprogram mode, and normal mode, wherein during the program mode or the reprogram mode, the control module enables the scan mode such that at least one of the plurality of data flow control state machines is programmed or reprogrammed.
25. The programmable ASIC of claim 23 , wherein at least one of the plurality of data flow control state machines further comprises:
a plurality of reserved scan enabled flip-flops operably coupled to the scan chain and is operably coupled to store at least one additional timing sequence instruction when the on-chip programmable state machine is reprogrammed.
26. The programmable ASIC of claim 23 , wherein the at least one instruction register further comprises a plurality of instruction registers, wherein each of the plurality of instruction registers stores a corresponding timing sequence instruction of a state machine algorithm.
27. The programmable ASIC of claim 26 , wherein the state machine logic circuitry further comprises:
an address generator operably coupled to address one of the plurality of instruction registers based on at least one of an external event and the corresponding timing sequence instruction of the one of the plurality of instruction registers or another one of the plurality of instruction registers.
28. The programmable ASIC of claim 23 , wherein the at least one timing sequence instruction comprises an initial count value field, a next address field, a conditional jump field, a load counter field, a count enable field, and control signals.
29. The programmable ASIC of claim 23 , wherein the plurality of scan enabled flip-flops is daisy chained together to serially receive and store the at least one timing sequence instruction.
30. The programmable ASIC of claim 23 further comprises:
a port operably coupled to the scan chain, wherein the at least one timing sequence instruction is programmed or reprogrammed into the plurality of scan enabled flip-flops via the scan chain.