Low noise amplifier with low current consumption
The invention relates to an amplifier circuit comprising supply terminals ( 12, 14 ) for supplying the circuit with first and second supply potentials (Vdd, Vss); a current path, which runs from the first supply terminal ( 12 ) via a first biased transistor (P 1 a , P 1 b ), a first node (K 1 a , K 1 b ), an input transistor (Q 1 a , Q 1 b ), a second node (K 2 a , K 2 b ) and a second biased transistor (N 1 a , N 1 b ) to the second supply terminal ( 14 ), wherein a control terminal of the input transistor is loaded with an input signal (inp-inn), and wherein the second node (K 2 a , K 2 a ) forms a pick-up in a resistor chain (R 2 a , R 1 , R 2 b ), at whose ends is supplied an output signal (outp-outn) as a voltage drop; and a feedback stage enabling the current to flow the resistor chain (R 2 a , R 1 , R 2 b ) dependent on the input signal (inp-inn) so that the current flowing through the input transistor (Q 1 a , Q 1 b ) is essentially independent of the input signal (inp-inn), wherein the feedback stage has a pair of complementarily coupled transistors (P 3 a , N 3 a , P 3 b , N 3 b ) with an intervening current output node (K 3 a , K 3 b ). To increase the scope of application of such an amplifier and achieve a low noise amplification at a low current consumption, provision is made, according to the invention, for the complementarily coupled transistors (P 3 a , N 3 a , P 3 b , N 3 b ) to be designed as FETs and the first node (K 1 a , K 1 b ) to be connected on the one hand via a third biased transistor (N 2 a , N 2 b ) to the second supply terminal ( 14 ) and on the other hand to a gate terminal of one (N 3 a , N 3 b ) of the complementarily coupled transistors (P 3 a , N 3 a , P 3 b , N 3 b ).
1. An amplifier circuit for amplifying an input signal (inp-inn) and transmitting the amplified signal as an output signal (outp-outn), comprising:
a first supply terminal ( 12 ) and a second supply terminal ( 14 ) for supplying the circuit with a first supply potential (Vdd) and a second supply potential (vss) respectively,
at least one current path which runs from the first supply terminal ( 12 ) via a first biased transistor (P 1 a , P 1 b ), a first circuit node (K 1 a , K 1 b ), an input transistor (Q 1 a , Q 1 b ), a second circuit node (K 2 a , K 2 b ) and a second biased transistor (N 1 a , N 1 b ) to the second supply terminal ( 14 ), wherein a control terminal of the input transistor is loaded with the input signal (inp-inn), and wherein the second circuit node (K 2 a , K 2 b ) forms a pick-up in a resistor chain (R 2 a , R 1 , R 2 b ) at whose ends the output signal (outp-outn) is supplied as a voltage drop, and
a feedback stage for enabling the current to flow through the resistor chain (R 2 a , R 1 , R 2 b ) dependent on the input signal (inp-inn) so that the current flowing through the input transistor (Q 1 a , Q 1 b ) is essentially independent of the input signal (inp-inn), where the feedback stage has a pair of transistors (P 3 a , N 3 a , P 3 b , N 3 b ) coupled for complementary operation with an intermediate output node (K 3 a , K 3 b ) for transmitting the current,
characterized in that the two complementarily coupled transistors (P 3 a , N 3 a , P 3 b , N 3 b ) of the feedback stage are designed as FETs, and in that the first circuit node (K 1 a , K 1 b ) is connected on the one hand via a third biased transistor (N 2 a , N 2 b ) to the second supply terminal ( 14 ), and on the other to a gate terminal of one (N 3 a , N 3 b ) of the two complementarily coupled transistors (P 3 a , N 3 a , P 3 b , N 3 b ).
2. The amplifier circuit according to claim 1 , wherein the first (P 1 a , P 1 b ) and second (N 1 a , N 1 b ) biased transistors are designed as FETs of different conductivity type.
3. The amplifier circuit according to claim 1 , wherein the third biased transistor (N 2 a , N 2 b ) is of the same conductivity type as the second biased transistor (N 1 a , N 1 b ).
4. The amplifier circuit according to claim 1 , wherein the connection of the first circuit node (K 1 a , K 1 b ) to the third biased transistor (N 2 a , N 2 b ) and to the gate terminal of the coupled transistor (N 3 a , N 3 b ) runs via a fourth biased transistor (P 2 a , P 2 b ).
5. The amplifier circuit according to claim 1 , wherein the input transistor (Q 1 a , Q 1 b ) is designed as a bipolar transistor.
6. The amplifier circuit according to claim 1 , wherein the two complementarily coupled transistors (P 3 a , N 3 a , P 3 b , N 3 b ) are of different conductivity types.
7. The amplifier circuit according to claim 1 , comprising two amplifier branches constructed symmetrically to each other, in which the resistor chain (R 2 a , R 1 , R 2 b ) forms a common part of both amplifier branches, wherein control terminals of the input transistors (Q 1 a , Q 1 b ) of the two amplifier branches are loaded with input potentials (inp, inn) of the differentially supplied input signal (inp-inn), and wherein the output signal (outp-outn) is supplied in differential form as a voltage drop at the common resistor chain (R 2 a , R 1 , R 2 b ).
8. The amplifier circuit according to claim 1 , wherein a supply voltage (Vdd-Vss) of less than 3V is provided.
9. An integrated circuit arrangement, comprising at least one amplifier circuit ( 10 ) according to claim 1 , wherein the integrated circuit arrangement also has an analog-digital converter connected downstream from the amplifier circuit ( 10 ) for converting the output signal (outp-outn) to a digital signal and a digital signal processing device, connected downstream from the analog-digital converter, for processing the digital signal.