Clock forming method for semiconductor integrated circuit and program product for the method
Regions G 1 to G 8 each including a predetermined number of flip-flops (FF) are divided into two groups. This dividing is performed so that the number of data connection channels intersected by a boundary is minimized. In the case of intersection of two data connection channels (A 1 , A 2 ), the number of data connection channels intersected by the boundary is two, the minimum number. After grouping of all the regions (G 1 to G 4, G 5 to G 8 ), clock tree synthesis (CTS) is performed. If clock forming is performed in this way, the increase in clock skew on an actual device can be limited and on-chip variation resistance can be increased.
1. A clock forming method for a semiconductor integrated circuit comprising the steps of:
a first step of dividing a circuit region into plural regions, each region having plural elements and connection channels for transferring data between the plurality of regions; and
a second step of synthesizing a clock tree by inserting clock drivers so that the elements in each region are connected in tree form,
wherein the number of connection channels intersected by a boundary is minimized when the circuit region is divided, and
wherein when the circuit region is divided, the positions of the elements contained in each region after dividing are within a predetermined distance from a centroid of the region.
2. The method according to claim 1 , wherein when the circuit region is divided, the boundary intersects the connection channels having a longer channel length or the connection channels having a larger number of logic stages with priority.
3. A clock forming method for a semiconductor integrated circuit, the method comprising:
a first step of dividing a circuit region into plural regions, each region having plural elements and connection channels for transferring data between the plurality of regions;
a second step of synthesizing a clock tree by inserting clock drivers so that the elements in each region are connected in tree form;
wherein the number of connection channels intersected by a boundary is minimized when the circuit region is divided, and
wherein when the circuit region is divided, the boundary does not intersect the connection channels having a setup margin equal to or smaller than a predetermined value.
4. A program product for causing a computer to execute a clock forming for a semiconductor integrated circuit:
a first step of dividing a circuit region into plural regions each region having plural elements and connection channels for transferring data between the regions; and
a second step of synthesizing a clock tree by inserting clock drivers so that the elements in each region are connected in tree form,
wherein the number of the connection channels intersected by a boundary is minimized when the circuit region is divided, and
wherein when the current region is divided, the positions of the elements contained in each region after dividing are within a predetermined distance from the centroid of the region or the boundary does not intersect the connection channels having a setup margin equal to or smaller than a predetermined value.
5. The program product according to claim 4 , wherein when the circuit region is divided, the boundary intersects the connection channels having a longer channel length or the connection channels having a larger number of logic stages with priority.