Semiconductor circuit, display device, and electronic appliance therewith
View Patent ↗It is an object of the invention to provide a semiconductor circuit requiring less number of transistors included in the semiconductor circuit and accurately serving as a shift register without providing a level shifter. The semiconductor circuit includes: an m (m is an arbitrary positive integer, m≧3) stage of a circuit group having a p-channel transistor, in which a first terminal is connected to a high potential power source, and an n-channel transistor, in which a first terminal is connected to a low potential power source; and an inverter circuit. A clock signal is input to a gate of the n-channel transistor in the (2n−1)th stage (n is an arbitrary integer, m≧2n≧2). An inverted clock signal is input to a gate of the n-channel transistor in the 2n-th stage (n is an arbitrary integer, m≧2n≧2).
1. A semiconductor circuit comprising:
m (m is an arbitrary positive integer, m≧3) stages, each of the m stages comprising a circuit group and an inverter circuit,
wherein the circuit group includes:
a p-channel transistor having a first terminal connected to a first potential power source;
a first n-channel transistor having a gate connected to a gate of the p-channel transistor and a first terminal connected to a second terminal of the p-channel transistor;
a second n-channel transistor having a first terminal connected to a second terminal of the first n-channel transistor and a second terminal connected to a second potential power source; and
an NAND circuit connected to the gate of the p-channel transistor, the gate of the first n-channel transistor, the second terminal of the p-channel transistor, and the first terminal of the first n-channel transistor,
wherein an input terminal of the inverter circuit is connected to the second terminal of the p-channel transistor and the first terminal of the first n-channel transistor,
wherein a clock signal is input to a gate of the second n-channel transistor in a (2n−1)th (n. is an arbitrary integer, m≧2n≧2) stage, and
wherein an inverted clock signal is input to a gate of the second n-channel transistor in a 2n-th stage.
2. A semiconductor circuit according to claim 1 ,
wherein a potential of the first potential power source is higher than a potential of the second potential power source.
3. A semiconductor circuit according to claim 1 ,
further comprising a-means for holding a potential between the circuit group and the inverter circuit.
4. A semiconductor circuit according to claim 1 ,
wherein the p-channel transistor, the first n-channel transistor, and the second n-channel transistor are thin film transistors formed on a glass substrate.
5. A semiconductor circuit according to claim 1 ,
wherein the p-channel transistor, the first n-channel transistor, and the second n-channel transistor are formed on a single crystalline substrate.
6. A semiconductor circuit according to claim 1 , wherein the semiconductor circuit is used for a shift register circuit.
7. A display device comprising the semiconductor circuit according to claim 1 .
8. An electronic appliance comprising the display device according to claim 7 .
9. The electronic appliance according to claim 8 is any one of a television receiver, a camera such as a video camera or a digital camera, a goggle type display, a navigation system, an audio reproducing device, a computer, a game machine, a mobile computer, a portable phone, a portable game machine, an electronic book, and an image reproducing device.
10. A display device comprising the semiconductor circuit according to claim 1 includes a liquid crystal element or an EL element.
11. A semiconductor circuit comprising:
m (m is an arbitrary positive integer, m≧3) stages, wherein each of the m stages comprising a first circuit group and a second circuit group,
wherein the first circuit group includes:
a first p-channel transistor having a first terminal connected to a first potential power source;
a first n-channel transistor having a gate connected to a gate of the first p-channel transistor and a first terminal connected to a second terminal of the first p-channel transistor; and
a second n-channel transistor having a first terminal connected to a second terminal of the first n-channel transistor and a second terminal connected to a second potential power source,
wherein the second circuit group includes:
a second p-channel transistor having a first terminal connected to the first potential power source;
a third n-channel transistor having a gate connected to the second terminal of the first p-channel transistor, the first terminal of the first n-channel transistor, and a gate of the second p-channel transistor, and a first terminal connected to a second terminal of the second p-channel transistor; and
a fourth n-channel transistor having a first terminal connected to a second terminal of the third n-channel transistor and a second terminal connected to the second potential power source,
wherein a clock signal is input to a gate of the second n-channel transistor in a (2n−1)th (n is an arbitrary integer, m≧2n≧2) stage, and a gate of the fourth n-channel transistor in the (2n−1)th stage, and
wherein an inverted clock signal is input to a gate of the second n-channel transistor in a 2n-th stage and a gate of the fourth n-channel transistor in the 2n-th stage.
12. A semiconductor circuit according claim 11 , wherein a potential of the first potential power source is higher than a potential of the second potential power source.
13. A semiconductor circuit according to claim 11 ,
wherein a high potential level of each of the clock signal and the inverted clock signal is the same as a potential of the first potential power source, and
wherein a low potential level of each of the clock signal and the inverted clock signal is higher than a potential of the second potential power source.
14. A semiconductor circuit according to claim 11 ,
further comprising a means for holding a potential between the first circuit group and the second circuit group.
15. A semiconductor circuit according to claim 11 , further comprising an NOR circuit in which the gate of the first p-channel transistor and the gate of the first n-channel transistor are connected, and the second terminal of the second p-channel transistor and the first terminal of the third n-channel transistor are connected.
16. A semiconductor circuit according to claim 11 ,
wherein the first to fourth n-channel transistors and the first and second p-channel transistors are thin film transistors formed on a glass substrate.
17. A semiconductor circuit according to claim 11 , wherein the first to fourth n-channel transistors and the first and second p-channel transistors are formed on a single crystalline substrate.
18. A semiconductor circuit according to claim 11 , wherein the semiconductor circuit is used for a shift register circuit.
19. A display device comprising the semiconductor circuit according to claim 11 .
20. An electronic appliance comprising the display device according to claim 19 .
21. The electronic appliance according to claim 20 is any one of a television receiver, a camera such as a video camera or a digital camera, a goggle type display, a navigation system, an audio reproducing device, a computer, a game machine, a mobile computer, a portable phone, a portable game machine, an electronic book, and an image reproducing device.
22. A display device comprising the semiconductor circuit according to claim 11 includes a liquid crystal element or an EL element.