Semiconductor integrated circuit device and I/O cell for the same
In a semiconductor integrated circuit device in which a plurality of I/O cells having level shift circuits are placed in an I/O region, two input/output cells respectively have four level shift circuits 11, 12 a to 12 c. A power supply cell, originally including only wiring for supply of a power supply voltage or a ground voltage, is additionally provided with three level shift circuits, which should originally be placed in the two input/output cells. The level shift circuits in the power supply cell are circuits asked for no high-speed operation and shared by the two input/output cells. This reduces the size of the two input/output cells and reduces the pitch of the I/O cells, permitting a larger number of required pins in a smaller area.
1. A semiconductor integrated circuit device comprising:
an internal logic circuit; and
a plurality of I/O cells placed in an I/O region located around the periphery of the internal logic circuit for securing interface with an external signal,
wherein at least one given I/O cell among the plurality of I/O cells has at least one level shift circuit, and
the level shift circuit for the given I/O cell is placed in a given location outside the given I/O cell and within the I/O region.
2. The device of claim 1 , wherein the level shift circuit for the given I/O cell, placed in the given location within the I/O region, is connected to the internal logic circuit via a line and also connected to the given I/O cell via another line.
3. The device of claim 2 , wherein the given I/O cell is an input/output cell for inputting/outputting a signal into/from the internal logic circuit from/to outside.
4. The device of claim 2 , wherein the given I/O cell is an output cell for outputting a signal from the internal logic circuit to outside.
5. The device of claim 2 , wherein the given I/O cell is an input cell for inputting a signal from outside into the internal logic circuit.
6. The device of claim 2 , wherein the level shift circuit for the given I/O cell is a level shift-up circuit that is not asked for high-speed operation equivalent to high-speed operation of the internal logic circuit and shifts the level of a signal from the internal logic circuit upwardly to an external signal voltage.
7. The device of claim 2 , wherein the I/O cells placed in the I/O region include a power supply cell, and
the given location within the I/O region in which the level shift circuit for the given I/O cell is placed is inside the power supply cell.
8. The device of claim 2 , wherein the I/O cells placed in the I/O region include a space cell for filling the gap between two given I/O cells, and
the given location within the I/O region in which the level shift circuit for the given I/O cell is placed is inside the space cell.
9. The device of claim 2 , wherein the I/O cells placed in the I/O region include a corner cell for linking a longitudinal part and a lateral part of the I/O region, and
the given location within the I/O region in which the level shift circuit for the given I/O cell is placed is inside the corner cell.
10. The device of claim 2 , wherein the I/O cells placed in the I/O region include an input cell for inputting a signal from outside into the internal logic circuit, and
the given location within the I/O region in which the level shift circuit for the given I/O cell is placed is inside the input cell.
11. The device of claim 1 , wherein the given I/O cell includes a control circuit that is connected to the level shift circuit and is not asked for high-speed operation, and
the control circuit is placed in a given location outside the given I/O cell and within the I/O region, together with the level shift circuit.
12. The device of claim 11 , wherein the control circuit is an output current switch control circuit for switching the output current capability from the given I/O cell.
13. The device of claim 11 , wherein the control circuit is an ON/OFF control circuit for switching whether to use or not a pull-up or pull-down function for fixing the potential at a terminal of the given I/O cell to “H” or “L”.
14. The device of claim 11 , wherein the control circuit is a pull-up/pull-down switch control circuit for fixing the potential at a terminal of the given I/O cell to “H” or “L”.
15. The device of claim 2 , wherein the given I/O cell comprises a plurality of given I/O cells,
the plurality of given I/O cells share the at least one level shift circuit, and
the shared level shift circuit is placed in a given location outside the given I/O cells and within the I/O region.
16. The device of claim 2 , wherein the level shift circuit placed in a given location within the I/O region is connected to the given I/O cell via a line arranged outside the I/O region.
17. The device of claim 2 , wherein the level shift circuit placed in a given location within the I/O region is connected to the given I/O cell via a line arranged to run above the I/O region.
18. An I/O cell placed in an I/O region located around the periphery of an internal logic circuit, the I/O cell comprising a level shift circuit for fulfilling a function other than its own function.
19. The I/O cell of claim 18 , further comprising a control circuit connected to the level shift circuit.
20. The I/O cell of claim 18 , wherein the I/O cell is a power supply cell.
21. The I/O cell of claim 18 , wherein the I/O cell is a space cell for filling the gap between two given I/O cells.
22. The I/O cell of claim 18 , wherein the I/O cell is a corner cell for linking a longitudinal part and a lateral part of the I/O region.
23. The I/O cell of claim 18 , wherein the I/O cell is an input cell for inputting a signal from outside into the internal logic circuit.