Semiconductor device capable of adjusting output impedance of external semiconductor device and output impedance adjusting method

1. A semiconductor device capable of adjusting an output impedance of a first output impedance adjustable output buffer of an external semiconductor device connectable to said semiconductor device, comprising:

a second output impedance adjustable output buffer;

a comparator adapted to compare a first output voltage of a first load circuit including said first output impedance adjustable output buffer with a second output voltage of a second load circuit including said second output impedance adjustable output buffer; and

an output impedance control circuit adapted to transmit an output signal of said comparator to said external semiconductor device to adjust the output impedance of said first output impedance adjustable output buffer, depending on the second output voltage, so that said first output voltage is made equal to said second output voltage.

2. The semiconductor device as set forth in claim 1 , further comprising:

a first pull-up/pull-down circuit included in said first load circuit; and

a second pull-up/pull-down circuit included in said second load circuit.

3. The semiconductor device as set forth in claim 2 , wherein said second pull-up/pull-down circuit is a replica of said first pull-up/pull-down circuit.

4. The semiconductor device as set forth in claim 2 , wherein each of said first and second pull-up/pull-down circuits comprises a pull-up resistor associated with a pull-up switch and a pull-down resistor associated with a pull-down switch, resistance values of said pull-up resistor and said pull-down resistor being larger than those of said first and second output impedance adjustable output buffers.

5. The semiconductor device as set forth in claim 2 , wherein said first load circuit comprises an external transmission line connected between said first output impedance adjustable output buffer and said first pull-up/pull-down circuit, and

wherein said second load circuit comprises an external replica resistor connected between said second output impedance adjustable output buffer and said second pull-up/pull-down circuit, a resistance value of said external replica resistor corresponding to a characteristic impedance of said external transmission line.

6. The semiconductor device as set forth in claim 5 , further comprising:

a first terminal connected to said second output impedance adjustable output buffer; and

a second terminal connected to said second pull-up/pull-down circuit, said external replica resistor being connected between said first and second terminals.

7. The semiconductor device as set forth in claim 2 , wherein said first load circuit comprises an external transmission line connected between said first output impedance adjustable output buffer and said first pull-up/pull-down circuit, and

wherein said second load circuit comprises a plurality of internal replica resistors associated with internal switches connected between said second output impedance adjustable output buffer and said second pull-up/pull-down circuit, a resistance value of at least one of said internal replica resistors selected by said internal switches corresponding to a characteristic impedance of said external transmission line.

8. The semiconductor device as set forth in claim 1 , further comprising a third output impedance adjustable output buffer connected to an internal circuit and included in said first load circuit,

said second output impedance adjustable output buffer being a replica of said third output impedance adjustable output buffer.

9. A method of semiconductor device capable of adjusting an output impedance of a first output impedance adjustable output buffer of an external semiconductor device connectable to a semiconductor device including a second output impedance adjustable output buffer, comprising:

comparing a first output voltage of a first load circuit including said first output impedance adjustable output buffer with a second output voltage of a second load circuit including said second output impedance adjustable output buffer, to generate a comparison signal; and

transmitting said comparison signal to said external semiconductor device to adjust the output impedance of said first output impedance adjustable output buffer,depending on the second output voltage, so that said first output voltage is made equal to said second output voltage.

10. The method as set forth in claim 9 , further comprising:

supplying a first current between said first output impedance adjustable output buffer and a first pull-up/pull-down circuit to obtain said first output voltage; and

supplying a second current between said second output impedance adjustable output buffer and a second pull-up/pull-down circuit to obtain said second output voltage.

11. The method as set forth in claim 10 , wherein each of said first and second pull-up/pull-down circuits comprises a pull-up resistor associated with a pull-up switch and a pull-down resistor associated with a pull-down switch, resistance values of said pull-up resistor and said pull-down resistor being larger than those of said first and second output impedance adjustable output buffers.

12. The method as set forth in claim 10 , wherein said first load circuit comprises an external transmission line connected between said first output impedance adjustable output buffer and said first pull-up/pull-down circuit, and

wherein said second load circuit comprises an external replica resistor connected between said second output impedance adjustable output buffer and said second pull-up/pull-down circuit, a resistance value of said external replica resistor corresponding to a characteristic impedance of said external transmission line.

13. The method as set forth in claim 12 , wherein said semiconductor device comprises:

a first terminal connected to said second output impedance adjustable output buffer; and

a second terminal connected to said second pull-up/pull-down circuit,

said external replica resistor being connected between said first and second terminals.

14. The semiconductor device as set forth in claim 10 , wherein said first load circuit comprises an external transmission line connected between said first output impedance adjustable output buffer and said first pull-up/pull-down circuit, and

wherein said second load circuit comprises a plurality of internal replica resistors associated with internal switches connected between said second output impedance adjustable output buffer and said second pull-up/pull-down circuit, a resistance value of at least one of said internal replica resistors selected by said internal switches corresponding to a characteristic impedance of said external transmission line.

15. The semiconductor device as set forth in claim 9 , wherein said semiconductor device comprises a third output impedance adjustable output buffer connected to an internal circuit and included in said first load circuit,

said second output impedance adjustable output buffer being a replica of said third output impedance adjustable output buffer.

16. The method as set forth in claim 15 , further comprising:

adjusting output impedances of said second and third output impedance adjustable output buffers simultaneously before said first output voltage is compared with said second output voltage; and

making said third output impedance adjustable output buffer in a high impedance state when said first output voltage is compared with said second output voltage.