Nonvolatile semiconductor memory device and method of testing thereof
A method of testing a nonvolatile semiconductor memory device is provided. The nonvolatile semiconductor memory device is provided with a memory cell of a field effect transistor type. The method includes: (A) performing erasing of the memory cell by using FN (Fowler-Nordheim) method; (B) performing programming back of the memory cell by using FN method, after the (A) step.
1. A nonvolatile semiconductor memory device comprising:
a memory cell of a field effect transistor type; and
a control circuit configured to control programming/erasing of said memory cell,
wherein in response to a test signal indicating a test mode, said control circuit performs erasing of said memory cell by using FN (Fowler-Nordheim) method and further performs programming back of said memory cell by using FN method.
2. The nonvolatile semiconductor memory device according to claim 1 ,
wherein in response to an erase signal indicating a normal erase mode different from said test mode, said control circuit performs erasing of said memory cell by using FN method and further performs programming back of said memory cell by using CHE (Channel Hot Electron) method.
3. The nonvolatile semiconductor memory device according to claim 2 ,
wherein said control circuit performs said erasing in said test mode for a longer time than said erasing in said normal erase mode.
4. The nonvolatile semiconductor memory device according to claim 1 ,
wherein in said test mode, said control circuit performs said erasing until said memory cell becomes a depression state.
5. The nonvolatile semiconductor memory device according to claim 1 ,
wherein said memory cell is formed on a well,
wherein in said programming back during said test mode, said control circuit applies positive potential to a control gate of said memory cell and applies negative potential to said well.
6. The nonvolatile semiconductor memory device according to claim 1 ,
further comprising a plurality of sectors formed on a plurality of wells, respectively,
wherein each of said plurality of sectors includes said memory cell,
wherein in said programming back during said test mode, said control circuit applies positive potential to a control gate of said memory cell included in a target sector of said plurality of sectors and applies negative potential to said plurality of wells in common.
7. A nonvolatile semiconductor memory device comprising:
a memory cell of a field effect transistor type; and
a control circuit configured to control programming/erasing of said memory cell,
wherein said control circuit switches a method of said programming between FN (Fowler-Nordheim) method and CHE (Channel Hot Electron) method, depending on an operation mode.
8. A method of testing a nonvolatile semiconductor memory device that includes a memory cell of a field effect transistor type, comprising:
(A) performing erasing of said memory cell by using FN (Fowler-Nordheim) method;
(B) performing programming back of said memory cell by using FN method, after said (A) step.
9. The method according to claim 8 ,
wherein said (A) step is performed until said memory cell becomes a depression state.
10. The method according to claim 8 ,
wherein said memory cell is formed on a well,
wherein in said (B) step, positive potential is applied to a control gate of said memory cell and negative potential is applied to said well.
11. The method according to claim 8 ,
wherein said nonvolatile semiconductor memory device is provided with a plurality of sectors formed on a plurality of wells, respectively, and each of said plurality of sectors includes said memory cell,
wherein in said (B) step, positive potential is applied to a control gate of said memory cell included in a target sector of said plurality of sectors, and negative potential is applied to said plurality of wells in common.