Method of fabricating strained-silicon transistors and strained-silicon CMOS transistors
A method of fabricating strained-silicon transistors includes providing a semiconductor substrate, in which the semiconductor substrate contains a gate structure thereon; performing an etching process to form two recesses corresponding to the gate structure within the semiconductor substrate; performing an oxygen flush on the semiconductor substrate; performing a cleaning process on the semiconductor substrate; and performing a selective epitaxial growth (SEG) to form an epitaxial layer in each recess for forming a source/drain region.
1. A method of fabricating strained-silicon transistors comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a gate structure thereon;
performing an etching process to form two recesses corresponding to the gate structure within the semiconductor substrate;
performing an oxygen flush on the semiconductor substrate;
utilizing a cleaning agent to perform a cleaning process on the semiconductor substrate, wherein the cleaning agent comprises sulfuric acid-hydrogen peroxide mixture (SPM) and RCA-1 for removing the remaining particles on the surface of the semiconductor substrate; and
performing a selective epitaxial growth (SEG) to form an epitaxial layer in each recess for forming a source/drain region.
2. The method of claim 1 , wherein gate structure further comprises:
a gate dielectric layer;
a gate disposed on the gate dielectric layer;
a cap layer formed on the gate; and
an oxide-nitride-oxide (ONO) offset spacer.
3. The method of claim 1 , wherein the oxygen flush is an in-situ process performed in the process chamber of the etching process.
4. The method of claim 1 , wherein the epitaxial layer comprises silicon germanium (Si x Ge 1−x , wherein 0<x<1).
5. The method of claim 1 , wherein the strained-silicon transistors comprises PMOS transistors.
6. A method of fabricating strained-silicon transistors comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a gate structure thereon;
performing an etching process to form two recesses corresponding to the gate structure within the semiconductor substrate;
utilizing a cleaning agent containing ozone to perform a cleaning process for removing the remaining etching particles from the surface of the semiconductor substrate, wherein the cleaning agent containing ozone comprises RCA-1, SPM, and deionized water containing ozone; and
performing a selective epitaxial growth (SEG) to form an epitaxial layer in each recess for forming a source/drain region.
7. The method of claim 6 , wherein gate structure further comprises:
a gate dielectric layer;
a gate disposed on the gate dielectric layer;
a cap layer formed on the gate; and
an oxide-nitride-oxide (ONO) offset spacer.
8. The method of claim 6 , wherein the cleaning process is an ex-situ process.
9. The method of claim 6 , wherein the epitaxial layer comprises silicon germanium (Si x Ge 1−x , wherein 0<x<1).
10. The method of claim 6 , wherein the strained-silicon transistors comprises PMOS transistors.
11. A method of fabricating strained-silicon CMOS transistors comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises an NMOS region and a PMOS region, and the NMOS region and the PMOS region further comprise an NMOS gate and a PMOS gate separately;
forming a sacrificial layer over the surface of the NMOS gate and the PMOS gate;
performing a first etching process to etch part of the sacrificial layer for forming a spacer around the PMOS gate;
performing a second etching process by utilizing the sacrificial layer, the PMOS gate and the spacer as a mask to form two recesses corresponding to the PMOS gate in the semiconductor substrate;
performing an oxygen flush on the semiconductor substrate;
performing a cleaning process on the semiconductor substrate;
performing a selective epitaxial growth (SEG) to form an epitaxial layer in each recess for forming a source/drain region of the PMOS transistor;
removing the sacrificial layer and the spacer; and
forming a source/drain region of the NMOS transistor.
12. The method of claim 11 , wherein the NMOS gate, the PMOS gate, and the semiconductor substrate comprises a gate dielectric layer in between and the surface of the NMOS gate and the PMOS gate comprises a cap layer.
13. The method of claim 12 , wherein the cap layer comprises silicon dioxide and silicon nitride, and the sacrificial layer comprises silicon oxide.
14. The method of claim 11 , wherein the oxygen flush is an in-situ process performed in the process chamber of the second etching process.
15. The method of claim 11 , wherein the cleaning agent of the cleaning process comprises sulfuric acid-hydrogen peroxide mixture (SPM) and RCA-1 for removing the remaining particles on the surface of the semiconductor substrate.
16. The method of claim 11 , wherein the epitaxial layer comprises silicon germanium (Si x Ge 1−x , wherein 0<x<1).
17. The method of claim 11 further comprising:
forming a photoresist on the NMOS region before the first etching process.
18. The method of claim 11 , wherein the process of forming the source/drain of the NMOS transistor comprises an ion implantation process.
19. A method of fabricating strained-silicon CMOS transistors comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises an NMOS region and a PMOS region, and the NMOS region and the PMOS region further comprise an NMOS gate and a PMOS gate separately;
forming a sacrificial layer over the surface of the NMOS gate and the PMOS gate;
performing a first etching process to etch part of the sacrificial layer for forming a spacer around the PMOS gate;
performing a second etching process by utilizing the sacrificial layer, the PMOS gate and the spacer as a mask to form two recesses corresponding to the PMOS gate in the semiconductor substrate;
utilizing a cleaning agent containing ozone to perform a cleaning process on the semiconductor substrate for removing the remaining particles on the surface of the semiconductor substrate;
performing a selective epitaxial growth (SEG) to form an epitaxial layer in each recess for forming a source/drain region of the PMOS transistor;
removing the sacrificial layer and the spacer; and
forming a source/drain region of the NMOS transistor.
20. The method of claim 19 , wherein the NMOS gate, the PMOS gate, and the semiconductor substrate comprises a gate dielectric layer in between and the surface of the NMOS gate and the PMOS gate comprises a cap layer.
21. The method of claim 19 , wherein the cap layer comprises silicon dioxide and silicon nitride, and the sacrificial layer comprises silicon oxide.
22. The method of claim 19 , wherein the cleaning agent containing ozone further comprises sulfuric acid-hydrogen peroxide mixture (SPM), RCA-1, and deionized water containing ozone.
23. The method of claim 19 , wherein the epitaxial layer comprises silicon germanium (Si x Ge 1−x , wherein 0<x<1).
24. The method of claim 19 , further comprising:
forming a photoresist on the NMOS region before the first etching process.
25. The method of claim 19 , wherein the process of forming the source/drain of the NMOS transistor comprises an ion implantation process.