Adaptive pixel for high dynamic range and disturbance detection and correction
View Patent ↗A new adaptive pixel architecture, folded-multiple-capture (FMC), integrates synchronous self-reset and multiple capture schemes and advantageously eliminates the requirement of a high-frame-rate sensor array, which is essential for conventional image sensors with high dynamic range. The FMC comprises a per-pixel analog-front-end (AFE), a fine analog-digital convertor (ADC) stage, and a digital-signal-processor/controller (DSPC) stage. The AFE performs programmable gain control, synchronous self-reset, sample-and-hold, and enables disturbance detection. In the AFE, a comparator compares an integrator output with a threshold voltage and produces a binary sequence accordingly. The ADC utilizes the binary sequence and the folded multiple capture signals to estimate photocurrent. An image sensor embodying the present invention adapts integration time to signal level, has minimal per-pixel hardware requirement, provides a very high dynamic range, about 120 dB or more, at high speed, about 1,000 frames/s or more, detects and corrects subframe disturbances, and consumes significantly less power.
1. An image sensor embodying a folded multiple capture architecture comprising:
a multi-bit analog-digital convertor (ADC) stage shared by a plurality of pixels;
a digital-signal-processor/controller (DSPC) stage coupled to said ADC stage; and
a per-pixel analog-front-end (AFE) coupled to said ADC and said DSPC; wherein said AFE having
an integrator that integrates photocurrent i ph received from a photodetector and outputs a corresponding digital value v(t) to said ADC; and
a comparator coupled to said integrator for periodically comparing said digital value v(t) with a threshold value V th synchronous with a clock signal; wherein
said comparator produces a 1 and resets said integrator every time said digital value v(t) is above said threshold value V th ; and wherein
said comparator produces a 0 every time said digital value v(t) is not above said threshold value V th , thereby generating a binary reset sequence;
wherein
said ADC globally captures said digital value v(t) multiple times; and wherein
based on outputs received from said AFE and said ADC, said DSPC estimates reset periods and effective integration times for each pixel coupled thereto, sorts captured values, detects anomalies, and estimates photocurrent.
2. The image sensor of claim 1 , wherein
said DSPC estimates said photocurrent with only non-saturated captures.
3. The image sensor of claim 2 , wherein
said DSPC utilizes a least-squares fit to estimate said photocurrent.
4. The image sensor of claim 1 , wherein
said ADC captures said digital value v(t) four times or less.
5. The image sensor of claim 4 , wherein
said ADC stage is optimized to consume about or less than 1 Watt of power.
6. The image sensor of claim 1 , wherein
said ADC is optimized for ultra-low power consumption.
7. The image sensor of claim 1 , wherein
said anomalies are caused by saturation, motion, disturbance, or a combination thereof.
8. The image sensor of claim 1 , wherein
said DSPC controls said AFE and said ADC so to adapt operation of said image sensor to one or more imaging conditions.
9. The image sensor of claim 1 , wherein
said threshold value V th and said clock signal are routed to all pixels of said image sensor.
10. The image sensor of claim 1 , further comprises
a memory buffer for storing said binary reset sequence and readout values.
11. A planar CMOS image sensor embodying the folded multiple capture architecture according to claim 1 .
12. A linear array embodying the folded multiple capture architecture according to claim 1 .
13. A focal plane array embodying the folded multiple capture architecture according to claim 1 .
14. A vertically integrated sensor array (VISA) embodying the folded multiple capture architecture according to claim 1 , said VISA comprising:
a photodetector layer;
said AFE, in which said AFE is coupled to said photodetector layer in one or more layers optimized for analog performance;
said ADC, in one or more layers optimized for mixed signal; and
said DSPC, in one or more layers optimized for logic performance and memory density.