IP Library › Granted Patent US 7,498,663
Granted Patent B2
US 7,498,663 · App. 10/921,172 · Granted Mar 3, 2009

Semiconductor integrated circuit

Assignee: Sharp Kabushiki Kaisha
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Quick Facts
Patent No.
US 7,498,663
App. No.
10/921,172
Granted
Mar 3, 2009
Kind
B2
Abstract

In a semiconductor integrated circuit ( 100 ) having a shielding film ( 1 ) formed by a material different from at least either of a semiconductor substrate ( 4 ) and an interlayer insulating film ( 7 ) in thermal expansion coefficient, the shielding film ( 1 ) has shielding portions ( 9 ) and openings ( 12 ), and at least either of a plurality of independent openings ( 12 a ) whose circumferences are surrounded by the shielding portions ( 9 ) and a plurality of independent shielding portions ( 11 ) whose circumferences are surrounded by the openings ( 12 ) is present and scattered on the entire surface of a chip. Or, a plurality of openings ( 12 ) are present on an optional straight line parallel with the surface ( 4 a ) of the semiconductor substrate ( 4 ) passing through a portion for shielding circuit devices ( 21 ) and circuit wirings ( 16 ) in the shielding portions ( 9 ).

Claims (64)

1. A semiconductor integrated circuit comprising:

a shielding film, substantially shielding passage of light to the semiconductor integrated circuit or substantially preventing electromagnetic radiation from being emitted from the semiconductor integrated circuit, formed by a material different from at least either of a semiconductor substrate and an interlayer insulating film in thermal expansion coefficient, wherein

said shielding film has shielding portions and openings such that at least either of a plurality of independent openings whose circumferences are surrounded by said shielding portions and a plurality of independent shielding portions whose circumferences are surrounded by said openings are present and scattered on the entire surface of said semiconductor substrate.

2. The semiconductor integrated circuit according to claim 1 , wherein

the ratio of an area on the surface of the semiconductor substrate occupied by said shielding portions is 61% or less.

3. The semiconductor integrated circuit according to claim 2 , wherein

the ratio of an area on the surface of the semiconductor substrate occupied by said shielding portions is 40% or more.

4. The semiconductor integrated circuit according to claim 1 , wherein

said shielding portions are respectively formed by a conductive metallic material, and

at least a part of said shielding portions is electrically connected to a fixed potential.

5. The semiconductor integrated circuit according to claim 1 , wherein

said shielding portions of said shielding film are respectively formed by a conductive metallic material and at least two layers of said shielding film are present on the surface of said semiconductor substrate,

at least a part of said shielding portions of each layer is electrically connected to a fixed potential,

said shielding films other than the uppermost layer one are a pattern formed so that one or more independent shielding portions whose circumferences are surrounded by said openings are present.

6. The semiconductor integrated circuit according to claim 1 , wherein

at least two layers of said shielding films are present on the surface of said semiconductor substrate and said shielding film of the upper-layer is a pattern formed so that said shielding portions shield said openings of said shielding film of the lower-layer.

7. The semiconductor integrated circuit according to claim 6 , wherein

the shielding film of the upper-layer is a pattern formed into an alternately repeating pattern in which at least either of the independent openings whose circumferences are surrounded by the shielding portions and the independent shielding portions whose circumferences are surrounded by the openings are alternately repeated in two directions orthogonal to each other, and

the shielding film of the lower-layer is said pattern formed into said alternately repeating pattern shifted in said two directions by the half of each respective pitch from the alternately repeating pattern of the upper-layer.

8. The semiconductor integrated circuit according to claim 1 , wherein

a circuit portion is formed on a surface of said semiconductor substrate, and

a rough face, which is formed on the back of said semiconductor substrate, for irregularly reflecting infrared radiation incoming toward the surface of said semiconductor substrate from the back of said semiconductor substrate.

9. The semiconductor integrated circuit according to claim 1 , wherein

at least one layer of said shielding film is present on both the surface and the back of said semiconductor substrate.

10. The semiconductor integrated circuit according to claim 1 , wherein

the back of said semiconductor substrate has a crystal defect density which is greater than the front of the semiconductor substrate.

11. A semiconductor integrated circuit comprising:

a shielding film, substantially shielding passage of light to the semiconductor integrated circuit or substantially preventing electromagnetic radiation from being emitted from the semiconductor integrated circuit, formed by a material different from at least either of a semiconductor substrate and an interlayer insulating film in thermal expansion coefficient, wherein

said shielding film has shielding portions and openings such that a plurality of the openings are present on an optional straight line parallel with a surface of said semiconductor substrate passing through a portion for shielding circuit devices and circuit wirings in said shielding portions.

12. The semiconductor integrated circuit according to claim 11 , wherein

the length of said shielding portions present on the straight line is 200 mm or less.

13. The semiconductor integrated circuit according to claim 11 , wherein

the ratio of an area on the surface of a semiconductor substrate occupied by said shielding portions is 61% or less.

14. The semiconductor integrated circuit according to claim 13 , wherein

the ratio of an area on the surface of the semiconductor substrate occupied by said shielding portions is 40% or less.

15. The semiconductor integrated circuit according to claim 11 , wherein

said shielding portions are respectively formed by a conductive metallic material, and

at least a part of said shielding portions is electrically connected to the fixed potential.

16. The semiconductor integrated circuit according to claim 11 , wherein

said shielding portions of said shielding film are respectively formed by a conductive metallic material and at least two layers of the shielding film are present on the surface of said semiconductor substrate,

at least a part of said shielding portions of each layer is electrically connected to a fixed potential, and

said shielding films other than the uppermost layer one are a pattern formed so that one or more independent shielding portions whose circumferences are surrounded by said openings are present.

17. The semiconductor integrated circuit according to claim 11 , wherein

at least two layers of said shielding film are present on the surface of said semiconductor substrate and said shielding film of the upper-layer is a pattern formed so that said shielding portions shield the openings of said shielding film of the lower-layer.

18. The semiconductor integrated circuit according to claim 17 , wherein

said shielding film of the upper-layer is a pattern formed into an alternately repeating pattern in which at least either of an independent opening whose circumference is surrounded by said shielding portions and an independent shielding portion whose circumference is surrounded by said openings is alternately repeated in two directions orthogonal to each other, and

said shielding film of the lower-layer is said pattern formed into said alternately repeating pattern shifted in said two directions by the half of a respective pitch from the alternately repeating pattern of the upper-layer.

19. The semiconductor integrated circuit according to claim 11 , wherein

a circuit portion is formed on the surface of said semiconductor substrate, and

a rough face, which is formed on the back of said semiconductor substrate, for irregularly reflecting infrared radiation incoming toward the surface of said semiconductor substrate from said back of said semiconductor substrate.

20. The semiconductor integrated circuit according to claim 11 , wherein

at least one layer of said shielding film is present on both the surface and the back of said semiconductor substrate.

21. The semiconductor integrated circuit according to claim 11 , wherein

the back of said semiconductor substrate has a crystal defect density which is greater than the front of the semiconductor substrate.

22. An IC card on which the semiconductor integrated circuit of claim 1 is mounted.

23. An IC card on which the semiconductor integrated circuit of claim 11 is mounted.

24. A semiconductor integrated circuit, comprising:

a semiconductor substrate;

at least one wiring layer formed on the semiconductor substrate;

an insulating film; and

a shielding film for protecting the at least one wiring layer from infrared radiation and preventing leakage of electromagnetic radiation from the semiconductor integrated circuit, wherein

said insulating film is formed between the shielding film and the semiconductor substrate,

said shielding film has shielding portions and openings, and

the ratio of shielding portions to said shielding film is 40% or more.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 19, 2004
From: HENMI, TAKUYA
To: SHARP KABUSHIKI KAISHA
Reel/Frame 015721/0950 →
Priority Claims (1)
JP 2003-295958 · Aug 20, 2003 · national
Continuity (1)
Related Publication 20050040500A1 · Feb 24, 2005