IP Library Granted Patent US 7,502,948
Granted Patent B2
US 7,502,948 · App. 11/026,705 · Granted Mar 10, 2009

Method, system, and apparatus for selecting a maximum operation point based on number of active cores and performance level of each of the active cores

Assignee: Intel Corporation
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Quick Facts
Patent No.
US 7,502,948
App. No.
11/026,705
Granted
Mar 10, 2009
Kind
B2
Abstract

Systems and methods of managing operating points provide for determining the number of active cores in a plurality of processor cores. A maximum operating point is selected for at least one of the active cores based on the number of active cores. In one embodiment, the number of active cores is determined by monitoring an ACPI processor power state signal of each of the plurality of cores.

Claims (25)

1. A method comprising:

determining a number of active cores in a plurality of processor cores, wherein the determining includes monitoring sleep state signal of each of the plurality of processor cores, and identifying whether each sleep state signal indicates that a corresponding core is active;

selecting a maximum operating point for at least one of the active cores based on the number of active cores, wherein the selecting is further based on a performance level of each of the active cores; and

generating a limit request based on the maximum operating point, wherein an operating parameter of the active cores is limited based on the limit request.

2. The method of claim 1 , wherein the monitoring includes monitoring an Advanced Configuration and Power Interface (ACPI) processor power state (Cx state) signal.

3. The method of claim 1 , wherein the selecting includes: searching a configuration table for an entry containing the number of active cores; and retrieving the maximum operating point from the entry.

4. The method of claim 3 , wherein the searching includes searching a basic input/output system (BIOS) configuration table.

5. The method of claim 1 , wherein the generating includes generating a limit request that specifies a maximum operating frequency.

6. The method of claim 5 , wherein generating the limit request further includes generating a limit request that specifies a maximum core voltage.

7. The method of claim 1 , further including determining the performance level of each of the active cores.

8. The method of claim 7 , wherein determining each performance level includes monitoring an Advanced Configuration and Power Interface (ACPI) performance state (Px state) signal of a corresponding core.

9. An apparatus comprising:

a plurality of processor cores; and

an activity module to determine a number of active cores in the plurality of processor cores, wherein the determining includes monitoring a sleep state signal of each of the plurality of processor cores, and identifying whether each sleep state signal indicates that a corresponding core is active, select a maximum operating point for at least one of the active cores based on the number of active cores, wherein the selecting is further based on a performance level of each of the active cores, and generate a limit request based on the maximum operating point, wherein an operating parameter of the active cores is limited based on limit request.

10. The apparatus of claim 9 , wherein the activity module is to monitor an Advanced Configuration and Power Interface (ACPI) processor power state (Cx state) signal.

11. The apparatus of claim 9 , wherein the activity module is to search a configuration table for an entry containing the number of active cores and retrieve the maximum operating point from the entry.

12. The apparatus of claim 11 , wherein the activity module is to search a basic input/output system (BIOS) configuration table to obtain the entry.

13. The apparatus of claim 9 , wherein the limit request is to specify a maximum operating frequency.

14. The apparatus of claim 13 , wherein the limit request is to further specify a maximum core voltage.

15. The apparatus of claim 9 , further including a processor package that contains the plurality of processor cores.

16. The apparatus of claim 9 , further including: a first processor package that contains a first subset of the plurality of processor cores; and a second processor package that contains a second subset of the plurality of processor cores.

17. A system comprising:

a small outline dual inline memory module (SODIMM); and

a processing architecture coupled to the SODIMM, the architecture including a plurality of processor cores and an activity module, the activity module to determine a number of active cores in the plurality of processor cores, wherein the determining includes monitoring a sleep state signal of each of the plurality of processor cores, and identifying whether each sleep state signal indicates that a corresponding core is active, select a maximum operating point for at least one of the active cores based on the number of active cores, wherein the selecting is further based on a performance level of each of the active cores, and generate a limit request based on the maximum operating point, wherein an operating parameter of the active cores is limited based on the limit request.

18. The system of claim 17 , further including a memory to store a configuration table, the activity module to search the configuration table for an entry containing the number of active cores and retrieve the maximum operating point from the entry.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 25, 2005
From: ROTEM, EFRAIM; LAMDAN, OREN; NAVEH, ALON
To: INTEL CORPORATION
Reel/Frame 016484/0431 →
Continuity (1)
Related Publication 20060149975A1 · Jul 6, 2006