IP Library › Granted Patent US 7,514,272
Granted Patent B2
US 7,514,272 · App. 11/717,791 · Granted Apr 7, 2009

Method of manufacturing ferroelectric memory device

Assignee: Seiko Epson Corporation
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Quick Facts
Patent No.
US 7,514,272
App. No.
11/717,791
Granted
Apr 7, 2009
Kind
B2
Abstract

A method of manufacturing a ferroelectric memory device includes: forming an active element on a substrate; forming an interlayer insulating layer on the substrate; forming an opening on the interlayer insulating layer and forming a contact plug inside the opening; forming a foundation layer above the substrate; and laminating, on the foundation layer, a first electrode, a ferroelectric layer, and a second electrode. In this method, the forming of the foundation layer includes: forming a first titanium layer having a thickness less than a depth of a recess; nitriding the first titanium layer into a first titanium nitride layer; forming a second titanium layer on the first titanium nitride layer so as to at least partially fill the recess remaining on the contact plug; nitriding the second titanium layer into a second titanium nitride layer, and polishing a surface of the second titanium nitride layer.

Claims (59)

1. A method of manufacturing a ferroelectric memory device, comprising:

forming an insulating layer having an opening above a substrate;

forming a plug in the opening, an upper surface of the plug being lower than an upper surface of the insulating layer;

forming a first layer including titanium on the insulating layer and the plug, the first layer having a recess;

forming a second layer including titanium on the first layer;

polishing the second layer,

forming a first electrode layer above the second layer;

forming a ferroelectric layer on the first electrode layer; and

forming a second electrode layer on the ferroelectric layer, wherein the forming of the first layer includes:

forming a first titanium layer with surface orientation on the plug and the insulating layer; and

converting the first titanium layer into a first nitride titanium layer with surface orientation (111) by nitriding the first titanium layer.

2. The method according to claim 1 , further comprising:

performing an ammonium plasma process to the insulating layer before the forming of the first layer.

3. The method according to claim 2 , wherein the performing of the ammonium plasma process includes:

exciting ammonium gas plasma; and

radiating the ammonium gas plasma onto the insulating layer.

4. The method according to claim 1 , wherein

the first layer is formed with a first thickness, and the first thickness is less than a distance from the upper surface of the plug to the upper surface of the insulating layer.

5. The method according to claim 1 , wherein

the second layer is formed so that the recess is filled with the second layer.

6. The method according to claim 1 , further comprising:

forming a barrier layer above the part of the first layer and the second layer after the polishing of the second layer.

7. The method according to claim 6 , further comprising:

forming a ferroelectric capacitor by etching the second electrode layer, the ferroelectric layer, the first electrode, the barrier layer, and the first layer.

8. The method according to claim 6 , wherein the barrier layer includes TiAIN.

9. The method according to claim 1 , further comprising:

forming a ferroelectric capacitor by etching the second electrode layer, the ferroelectric layer, the first electrode layer and the first layer.

10. The method according to claim 1 , wherein the substrate includes a transistor having a source and a drain.

11. The method according to claim 10 , wherein the plug is electrically connected to the source or the drain.

12. The method according to claim 1 , wherein the second layer includes a third nitride titanium layer, and the third nitride titanium layer is formed by a reactive sputtering method.

13. A method of manufacturing a ferroelectric memory device, comprising:

forming an insulating layer having an opening above a substrate;

forming a plug in the opening, an upper surface of the plug being lower than an upper surface of the insulating layer;

forming a first layer including titanium on the insulating layer and the plug, the first layer having a recess;

forming a second layer including titanium on the first layer;

polishing the second layer;

forming a first electrode layer above the second layer;

forming a ferroelectric layer on the first electrode layer; and

forming a second electrode layer on the ferroelectric layer, wherein

the forming of the second layer includes:

forming a second titanium layer with surface orientation (001) on the first layer; and

converting the second titanium layer into a second nitride titanium layer with surface orientation (111) by nitriding the second titanium layer.

14. The method according to claim 13 , further comprising:

performing an ammonium plasma process to the insulating layer before the forming of the first layer.

15. The method according to claim 14 , wherein the performing of the ammonium plasma process includes:

exciting ammonium gas plasma; and

radiating the ammonium gas plasma onto the insulating layer.

16. The method according to claim 13 , wherein the first layer is formed with a first thickness, and the first thickness is less than a distance from the upper surface of the plug to the upper surface of the insulating layer.

17. The method according to claim 13 , wherein the second layer is formed so that the recess is filled with the second layer.

18. The method according to claim 13 , further comprising:

forming a barrier layer above the part of the first layer and the second layer after the polishing of the second layer.

19. The method according to claim 18 , further comprising:

forming a ferroelectric capacitor by etching the second electrode layer, the ferroelectric layer, the first electrode layer, the barrier layer, and the first layer.

20. The method according to claim 18 , wherein the barrier layer includes TiAIN.

21. The method according to claim 13 , further comprising:

forming a ferroelectric capacitor by etching the second electrode layer, the ferroelectric layer, the first electrode layer, and the first layer.

22. The method according to claim 13 , wherein the substrate includes a transistor having a source and a drain.

23. The method according to claim 22 , wherein the plug is electrically connected to the source or the drain.

24. The method according to claim 13 , wherein the second layer includes a third nitride titanium layer, and the third nitride titanium layer is formed by a reactive sputtering method.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 13, 2020
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR MEMORY SOLUTION LIMITED
Reel/Frame 053195/0249 →
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 15, 2016
From: SEIKO EPSON CORPORATION
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 037987/0149 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 13, 2007
From: FUKADA, SHINICHI; MITSUI, HIROYUKI
To: SEIKO EPSON CORPORATION
Reel/Frame 019117/0523 →
Priority Claims (1)
JP 2006-069100 · Mar 14, 2006 · national
Continuity (1)
Related Publication 20070218569A1 · Sep 20, 2007