Structures and methods to store information representable by a multiple bit binary word in electrically erasable, programmable read-only memories (EEPROM)
Innovative structures and methods to store information capable of being represented by an n-bit binary word in electrically erasable Programmable Read-Only memories (EEPROM) are disclosed. To program a state below the highest threshold voltage for an N-type Field Effect Transistor (NFET) based EEPROM, the stored charge in the floating gate for the highest threshold voltage is erased down to the desired threshold voltage level of the EEPROM by applying an appropriate voltage to the control gate and drain of the NFET. The erase-down uses drain-avalanche-hot hole injection (DAHHI) for the NFET memory device to achieve the precise threshold voltage desired for the NFET EEPROM device. The method takes advantage of the self-convergent mechanism from the DAHHI current in the device, when the device reaches a steady state. For a “READ” operation, a read voltage is applied to the control gate and the drain is connected by a current load to the positive voltage supply. Using the distinctive threshold voltage associated with the different stored charges, the output voltage from the drain is distinctively recognized and converted back to the original n-bit word. A similar method for a PFET EEPROM is also disclosed.
1. A structure for storing in a single nonvolatile memory cell any one of the values capable of being represented by a given number of bits, comprising:
a nonvolatile memory cell having an FET with a control gate, a source region, and a drain region, and having a resistor one end of which is coupled to said drain region and the other end of which is capable of being coupled to a source of a high voltage; and
said control gate being capable of being coupled to a source of multiple values of voltages, each of said voltages representing a value of multi-bits to be stored in said nonvolatile memory cell.
2. The structure of claim 1 , wherein said nonvolatile memory comprises an NFET based electrically erasable programmable read-only memory (EEPROM).
3. The structure of claim 1 , wherein the amplitudes of voltages provided by said source of multiple values of voltages are different.
4. A single nonvolatile memory cell, comprising:
a field effect transistor having a drain, a source, a floating gate and a control gate;
a resistor with a first end and a second end, said first end being coupled to said drain and said second end being capable of being coupled to a source of a low voltage; and
a source of multiple voltage levels capable of being coupled to said control gate for providing a selected voltage representable by multiple-bits to be stored in said nonvolatile memory cell.
5. The structure of claim 4 , wherein said nonvolatile memory cell comprises a PFET-based electrically erasable programmable read-only memory (EEPROM).
6. The structure of claim 4 , wherein the amplitude of each voltage provided by said source of multiple voltage levels differs from the amplitudes of said other voltages provided by said source.
7. A method for storing information capable of being represented by a multiple bit binary word in a single nonvolatile memory cell, comprising:
programming a nonvolatile memory cell to the highest threshold voltage to which said nonvolatile memory cell can be programmed by applying a high voltage to both a control gate and to a drain electrode of said nonvolatile memory cell; and
erasing down from said highest threshold voltage to a specific threshold voltage by applying a voltage selected from a plurality of different voltages to said control gate by selecting a resistor having an appropriate value of resistance to couple between said drain electrode and a source of said high-voltage.
8. The method of claim 7 , wherein said nonvolatile memory cell comprises an NFET-based electrically erasable programmable read-only memory (EEPROM).
9. The method of claim 7 , wherein the amplitudes of said voltages are different and vary from a low voltage to said high voltage.
10. A method for storing any one of a plurality of voltages, each voltage capable of being represented by a multiple bit binary word, in a single nonvolatile memory cell having a substrate, a source, a drain, and a control gate, comprising:
programming said nonvolatile memory cell to a most negative threshold voltage by applying a high voltage both to said source and to said substrate; and
erasing up from said most negative threshold voltage to a specific negative threshold voltage level by applying a voltage selected form a plurality of different voltages to said control gate by selecting a resistor having an appropriate value of resistance to couple between said drain electrode and said source of high voltage.
11. The method of claim 10 , wherein said nonvolatile memory comprises a PFET-based electrically erasable programmable read-only memory (EEPROM).
12. The method of claim 10 , wherein the amplitudes of said voltages are different and vary from a low voltage to said high voltage.