MOS-transistor on SOI substrate with source via
In an inventive MOS transistor having a source region, a drain region and a channel region, which are formed in a semiconductor layer of an SOI substrate, which has a semiconductor substrate below the semiconductor layer and an isolation layer between semiconductor layer and semiconductor substrate, the drain or source region is electrically connected to a backside contact on a side of the semiconductor substrate facing away from the isolation layer by a via running through the semiconductor substrate. The central idea of the present invention is to obtain an easy contactability of an MOS transistor without limitations in the application spectrum, by leading a via either from the source or the drain region across both the isolation layer and the semiconductor substrate to a backside contact, to be electrically connected to the same, since thereby the requirements of the material properties of the semiconductor substrates, such as doping and conductivity, are unnecessary or reduced.
1. An MOS transistor having a source region, a drain region and a channel region formed in a semiconductor layer of an SOI substrate having a semiconductor substrate below the semiconductor layer and an isolation layer between semiconductor layer and semiconductor substrate, wherein one of the drain or source region is electrically connected to a backside contact formed on the side of the semiconductor substrate facing away from the isolation layer through a via running through the semiconductor substrate, wherein the via has an opening filled with a conductive material running from the one of the drain or source region at least through the isolation layer, and wherein a portion of the via extending through the semiconductor substrate has a greater conductivity than surrounding portions of the semiconductor substrate, wherein the portion of the via extending through the semiconductor substrate comprises a continuation of the opening filled with a conductive material so that the opening runs to the side of the semiconductor substrate facing away from the isolation layer, and so that a continuous path of the conductive material extends through the via from said side of the semiconductor substrate to a side of the semiconductor layer facing away from the isolation layer, the conductive material comprising metal and the semiconductor substrate having a doping concentration lying between 1×10 12 and 1×10 16 cm −3 .
2. An MOS transistor having a source region, a drain region and a channel region formed in a semiconductor layer of an SOI substrate having a semiconductor substrate below the semiconductor layer and an isolation layer between semiconductor layer and semiconductor substrate, wherein one of the drain or source region is electrically connected to a backside contact formed on the side of the semiconductor substrate facing away from the isolation layer through a via running through the semiconductor substrate, wherein the via has an opening filled with a conductive material running from the one of the drain or source region at least through the isolation layer, and wherein a portion of the via extending through the semiconductor substrate has a greater conductivity than surrounding portions of the semiconductor substrate, wherein the portion of the via extending through the semiconductor substrate comprises an increased doping concentration in the semiconductor substrate running from the opening through the semiconductor substrate to the backside contact, and wherein the increased doping concentration is approximately between 1×10 16 and 3×10 20 1/cm 3 , while a main doping concentration of the substrate lies between 1×10 12 and 1×10 16 1/cm 3 .
3. The MOS transistor according to claim 1 , wherein the one of the drain or source region is the source region, and the MOS transistor further comprises a drain terminal and a gate terminal, the gate terminal disposed on a side facing away from the SOI substrate, and wherein the gate terminal is coupled to the channel region and the drain terminal is electrically connected to the drain region.
4. An RF power transistor having a plurality of transistors, each having a source region, a drain region and a channel region formed in a semiconductor layer of an SOI substrate having a semiconductor substrate below the semiconductor layer and an isolation layer between semiconductor layer and semiconductor substrate, wherein one of the drain or source region is electrically connected to a backside contact formed on the side of the semiconductor substrate facing away from the isolation layer through a via running through the semiconductor substrate, wherein the via has an opening filled with a conductive material running from the one of the drain or source region at least through the isolation layer, and wherein a portion of the via extending through the semiconductor substrate has a greater conductivity than surrounding portions of the semiconductor substrate, wherein the portion of the via extending through the semiconductor substrate comprises a continuation of the opening filled with a conductive material so that the opening inns to the side of the semiconductor substrate facing away from the isolation layer, and so that a continuous path of the conductive material extending through the via from said side of the semiconductor substrate to a side of the semiconductor layer facing away from the isolation layer, the conductive material comprising metal and the semiconductor substrate having a doping concentration lying between 1×10 12 and 1×10 16 cm −3 , wherein the plurality of transistors are arranged juxtaposed to each other, and the RF power transistor comprises drain and gate terminals arranged in an interdigitated manner, the drain terminals and the gate terminals electrically connected at opposing ends so that each drain terminal is electrically connected to the drain regions of the neighboring transistor, and wherein the one of the drain or source region is the source region, so that each via is electrically connected to the source region of two neighboring transistors, and the backside contact is commonly connected to the source region of all transistors.
5. An RF power transistor having a plurality of transistors, each having a source region, a drain region and a channel region formed in a semiconductor layer of an SOI substrate having a semiconductor substrate below the semiconductor layer and an isolation layer between semiconductor layer and semiconductor substrate, wherein one of the drain or source region is electrically connected to a backside contact formed on the side of the semiconductor substrate facing away from the isolation layer through a via running through the semiconductor substrate, wherein the via has an opening filled with a conductive material running from the one of the drain or source region at least through the isolation layer, and wherein a portion of the via extending through the semiconductor substrate has a greater conductivity than surrounding portions of the semiconductor substrate, wherein the portion of the via extending through the semiconductor substrate comprises an increased doping portion of the semiconductor substrate running from the opening through the semiconductor substrate to the backside contact, and wherein the increased doping portion has a doping concentration of approximately between 1×10 16 and 3×10 20 1/cm 3 , while the main doping concentration of the substrate lies between 1×10 12 and 1×10 16 1/cm 3 , wherein the plurality of transistors are arranged juxtaposed to each other, and the RF power transistor comprises drain and gate terminals arranged in an interdigitated manner, the drain terminals and the gate terminals electrically connected at opposing ends so that each drain terminal is electrically connected to the drain regions of the neighboring transistor, and wherein the one of the drain or source region is the source region, so that each via is electrically connected to the source region of two neighboring transistors, and the backside contact is commonly connected to the source region of all transistors.